123 lines
3.7 KiB
YAML
123 lines
3.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Renesas Clock Pulse Generator / Module Standby and Software Reset
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description: |
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On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
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and MSSR (Module Standby and Software Reset) blocks are intimately connected,
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and share the same register block.
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They provide the following functionalities:
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- The CPG block generates various core clocks,
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- The MSSR block provides two functions:
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1. Module Standby, providing a Clock Domain to control the clock supply
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to individual SoC devices,
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2. Reset Control, to perform a software reset of individual SoC devices.
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properties:
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compatible:
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enum:
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- renesas,r7s9210-cpg-mssr # RZ/A2
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- renesas,r8a7742-cpg-mssr # RZ/G1H
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- renesas,r8a7743-cpg-mssr # RZ/G1M
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- renesas,r8a7744-cpg-mssr # RZ/G1N
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- renesas,r8a7745-cpg-mssr # RZ/G1E
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- renesas,r8a77470-cpg-mssr # RZ/G1C
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- renesas,r8a774a1-cpg-mssr # RZ/G2M
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- renesas,r8a774b1-cpg-mssr # RZ/G2N
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- renesas,r8a774c0-cpg-mssr # RZ/G2E
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- renesas,r8a774e1-cpg-mssr # RZ/G2H
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- renesas,r8a7790-cpg-mssr # R-Car H2
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- renesas,r8a7791-cpg-mssr # R-Car M2-W
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- renesas,r8a7792-cpg-mssr # R-Car V2H
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- renesas,r8a7793-cpg-mssr # R-Car M2-N
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- renesas,r8a7794-cpg-mssr # R-Car E2
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- renesas,r8a7795-cpg-mssr # R-Car H3
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- renesas,r8a7796-cpg-mssr # R-Car M3-W
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- renesas,r8a77961-cpg-mssr # R-Car M3-W+
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- renesas,r8a77965-cpg-mssr # R-Car M3-N
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- renesas,r8a77970-cpg-mssr # R-Car V3M
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- renesas,r8a77980-cpg-mssr # R-Car V3H
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- renesas,r8a77990-cpg-mssr # R-Car E3
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- renesas,r8a77995-cpg-mssr # R-Car D3
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- renesas,r8a779a0-cpg-mssr # R-Car V3U
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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maxItems: 2
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items:
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enum:
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- extal # All
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- extalr # Most R-Car Gen3 and RZ/G2
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- usb_extal # Most R-Car Gen2 and RZ/G1
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'#clock-cells':
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description: |
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- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
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and a core clock reference, as defined in
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<dt-bindings/clock/*-cpg-mssr.h>
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- For module clocks, the two clock specifier cells must be "CPG_MOD" and
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a module number, as defined in the datasheet.
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const: 2
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'#power-domain-cells':
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description:
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SoC devices that are part of the CPG/MSSR Clock Domain and can be
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power-managed through Module Standby should refer to the CPG device node
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in their "power-domains" property, as documented by the generic PM Domain
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bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
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const: 0
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'#reset-cells':
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description:
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The single reset specifier cell must be the module number, as defined in
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the datasheet.
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const: 1
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if:
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not:
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properties:
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compatible:
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items:
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enum:
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- renesas,r7s9210-cpg-mssr
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then:
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required:
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- '#reset-cells'
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a7795-cpg-mssr";
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reg = <0xe6150000 0x1000>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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