480 lines
14 KiB
C
480 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef _LINUX_QCOM_GENI_SE
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#define _LINUX_QCOM_GENI_SE
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#include <linux/interconnect.h>
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/**
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* enum geni_se_xfer_mode: Transfer modes supported by Serial Engines
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*
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* @GENI_SE_INVALID: Invalid mode
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* @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO
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* by programmed IO method
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* @GENI_SE_DMA: Serial Engine DMA mode. Data is transferred
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* with SE by DMAengine internal to SE
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* @GENI_GPI_DMA: GPI DMA mode. Data is transferred using a DMAengine
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* configured by a firmware residing on a GSI engine. This DMA name is
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* interchangeably used as GSI or GPI which seem to imply the same DMAengine
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*/
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enum geni_se_xfer_mode {
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GENI_SE_INVALID,
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GENI_SE_FIFO,
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GENI_SE_DMA,
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GENI_GPI_DMA,
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};
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/* Protocols supported by GENI Serial Engines */
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enum geni_se_protocol_type {
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GENI_SE_NONE,
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GENI_SE_SPI,
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GENI_SE_UART,
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GENI_SE_I2C,
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GENI_SE_I3C,
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};
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struct geni_wrapper;
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struct clk;
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enum geni_icc_path_index {
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GENI_TO_CORE,
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CPU_TO_GENI,
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GENI_TO_DDR
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};
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struct geni_icc_path {
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struct icc_path *path;
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unsigned int avg_bw;
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};
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/**
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* struct geni_se - GENI Serial Engine
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* @base: Base Address of the Serial Engine's register block
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* @dev: Pointer to the Serial Engine device
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* @wrapper: Pointer to the parent QUP Wrapper core
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* @clk: Handle to the core serial engine clock
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* @num_clk_levels: Number of valid clock levels in clk_perf_tbl
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* @clk_perf_tbl: Table of clock frequency input to serial engine clock
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* @icc_paths: Array of ICC paths for SE
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*/
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struct geni_se {
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void __iomem *base;
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struct device *dev;
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struct geni_wrapper *wrapper;
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struct clk *clk;
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unsigned int num_clk_levels;
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unsigned long *clk_perf_tbl;
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struct geni_icc_path icc_paths[3];
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};
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/* Common SE registers */
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#define GENI_FORCE_DEFAULT_REG 0x20
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#define SE_GENI_STATUS 0x40
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#define GENI_SER_M_CLK_CFG 0x48
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#define GENI_SER_S_CLK_CFG 0x4c
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#define GENI_IF_DISABLE_RO 0x64
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#define GENI_FW_REVISION_RO 0x68
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#define SE_GENI_CLK_SEL 0x7c
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#define SE_GENI_DMA_MODE_EN 0x258
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#define SE_GENI_M_CMD0 0x600
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#define SE_GENI_M_CMD_CTRL_REG 0x604
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#define SE_GENI_M_IRQ_STATUS 0x610
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#define SE_GENI_M_IRQ_EN 0x614
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#define SE_GENI_M_IRQ_CLEAR 0x618
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#define SE_GENI_S_CMD0 0x630
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#define SE_GENI_S_CMD_CTRL_REG 0x634
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#define SE_GENI_S_IRQ_STATUS 0x640
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#define SE_GENI_S_IRQ_EN 0x644
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#define SE_GENI_S_IRQ_CLEAR 0x648
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#define SE_GENI_TX_FIFOn 0x700
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#define SE_GENI_RX_FIFOn 0x780
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#define SE_GENI_TX_FIFO_STATUS 0x800
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#define SE_GENI_RX_FIFO_STATUS 0x804
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#define SE_GENI_TX_WATERMARK_REG 0x80c
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#define SE_GENI_RX_WATERMARK_REG 0x810
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#define SE_GENI_RX_RFR_WATERMARK_REG 0x814
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#define SE_GENI_IOS 0x908
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#define SE_DMA_TX_IRQ_STAT 0xc40
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#define SE_DMA_TX_IRQ_CLR 0xc44
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#define SE_DMA_TX_FSM_RST 0xc58
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#define SE_DMA_RX_IRQ_STAT 0xd40
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#define SE_DMA_RX_IRQ_CLR 0xd44
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#define SE_DMA_RX_FSM_RST 0xd58
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#define SE_HW_PARAM_0 0xe24
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#define SE_HW_PARAM_1 0xe28
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/* GENI_FORCE_DEFAULT_REG fields */
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#define FORCE_DEFAULT BIT(0)
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/* GENI_STATUS fields */
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#define M_GENI_CMD_ACTIVE BIT(0)
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#define S_GENI_CMD_ACTIVE BIT(12)
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/* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
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#define SER_CLK_EN BIT(0)
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#define CLK_DIV_MSK GENMASK(15, 4)
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#define CLK_DIV_SHFT 4
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/* GENI_IF_DISABLE_RO fields */
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#define FIFO_IF_DISABLE (BIT(0))
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/* GENI_FW_REVISION_RO fields */
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#define FW_REV_PROTOCOL_MSK GENMASK(15, 8)
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#define FW_REV_PROTOCOL_SHFT 8
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/* GENI_CLK_SEL fields */
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#define CLK_SEL_MSK GENMASK(2, 0)
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/* SE_GENI_DMA_MODE_EN */
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#define GENI_DMA_MODE_EN BIT(0)
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/* GENI_M_CMD0 fields */
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#define M_OPCODE_MSK GENMASK(31, 27)
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#define M_OPCODE_SHFT 27
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#define M_PARAMS_MSK GENMASK(26, 0)
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/* GENI_M_CMD_CTRL_REG */
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#define M_GENI_CMD_CANCEL BIT(2)
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#define M_GENI_CMD_ABORT BIT(1)
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#define M_GENI_DISABLE BIT(0)
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/* GENI_S_CMD0 fields */
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#define S_OPCODE_MSK GENMASK(31, 27)
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#define S_OPCODE_SHFT 27
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#define S_PARAMS_MSK GENMASK(26, 0)
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/* GENI_S_CMD_CTRL_REG */
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#define S_GENI_CMD_CANCEL BIT(2)
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#define S_GENI_CMD_ABORT BIT(1)
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#define S_GENI_DISABLE BIT(0)
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/* GENI_M_IRQ_EN fields */
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#define M_CMD_DONE_EN BIT(0)
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#define M_CMD_OVERRUN_EN BIT(1)
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#define M_ILLEGAL_CMD_EN BIT(2)
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#define M_CMD_FAILURE_EN BIT(3)
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#define M_CMD_CANCEL_EN BIT(4)
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#define M_CMD_ABORT_EN BIT(5)
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#define M_TIMESTAMP_EN BIT(6)
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#define M_RX_IRQ_EN BIT(7)
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#define M_GP_SYNC_IRQ_0_EN BIT(8)
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#define M_GP_IRQ_0_EN BIT(9)
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#define M_GP_IRQ_1_EN BIT(10)
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#define M_GP_IRQ_2_EN BIT(11)
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#define M_GP_IRQ_3_EN BIT(12)
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#define M_GP_IRQ_4_EN BIT(13)
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#define M_GP_IRQ_5_EN BIT(14)
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#define M_IO_DATA_DEASSERT_EN BIT(22)
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#define M_IO_DATA_ASSERT_EN BIT(23)
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#define M_RX_FIFO_RD_ERR_EN BIT(24)
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#define M_RX_FIFO_WR_ERR_EN BIT(25)
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#define M_RX_FIFO_WATERMARK_EN BIT(26)
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#define M_RX_FIFO_LAST_EN BIT(27)
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#define M_TX_FIFO_RD_ERR_EN BIT(28)
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#define M_TX_FIFO_WR_ERR_EN BIT(29)
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#define M_TX_FIFO_WATERMARK_EN BIT(30)
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#define M_SEC_IRQ_EN BIT(31)
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#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \
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M_IO_DATA_DEASSERT_EN | \
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M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
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M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
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M_TX_FIFO_WR_ERR_EN)
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/* GENI_S_IRQ_EN fields */
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#define S_CMD_DONE_EN BIT(0)
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#define S_CMD_OVERRUN_EN BIT(1)
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#define S_ILLEGAL_CMD_EN BIT(2)
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#define S_CMD_FAILURE_EN BIT(3)
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#define S_CMD_CANCEL_EN BIT(4)
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#define S_CMD_ABORT_EN BIT(5)
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#define S_GP_SYNC_IRQ_0_EN BIT(8)
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#define S_GP_IRQ_0_EN BIT(9)
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#define S_GP_IRQ_1_EN BIT(10)
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#define S_GP_IRQ_2_EN BIT(11)
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#define S_GP_IRQ_3_EN BIT(12)
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#define S_GP_IRQ_4_EN BIT(13)
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#define S_GP_IRQ_5_EN BIT(14)
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#define S_IO_DATA_DEASSERT_EN BIT(22)
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#define S_IO_DATA_ASSERT_EN BIT(23)
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#define S_RX_FIFO_RD_ERR_EN BIT(24)
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#define S_RX_FIFO_WR_ERR_EN BIT(25)
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#define S_RX_FIFO_WATERMARK_EN BIT(26)
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#define S_RX_FIFO_LAST_EN BIT(27)
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#define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \
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S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN)
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/* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
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#define WATERMARK_MSK GENMASK(5, 0)
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/* GENI_TX_FIFO_STATUS fields */
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#define TX_FIFO_WC GENMASK(27, 0)
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/* GENI_RX_FIFO_STATUS fields */
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#define RX_LAST BIT(31)
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#define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28)
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#define RX_LAST_BYTE_VALID_SHFT 28
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#define RX_FIFO_WC_MSK GENMASK(24, 0)
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/* SE_GENI_IOS fields */
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#define IO2_DATA_IN BIT(1)
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#define RX_DATA_IN BIT(0)
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/* SE_DMA_TX_IRQ_STAT Register fields */
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#define TX_DMA_DONE BIT(0)
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#define TX_EOT BIT(1)
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#define TX_SBE BIT(2)
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#define TX_RESET_DONE BIT(3)
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/* SE_DMA_RX_IRQ_STAT Register fields */
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#define RX_DMA_DONE BIT(0)
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#define RX_EOT BIT(1)
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#define RX_SBE BIT(2)
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#define RX_RESET_DONE BIT(3)
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#define RX_FLUSH_DONE BIT(4)
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#define RX_GENI_GP_IRQ GENMASK(10, 5)
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#define RX_GENI_CANCEL_IRQ BIT(11)
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#define RX_GENI_GP_IRQ_EXT GENMASK(13, 12)
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/* SE_HW_PARAM_0 fields */
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#define TX_FIFO_WIDTH_MSK GENMASK(29, 24)
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#define TX_FIFO_WIDTH_SHFT 24
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#define TX_FIFO_DEPTH_MSK GENMASK(21, 16)
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#define TX_FIFO_DEPTH_SHFT 16
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/* SE_HW_PARAM_1 fields */
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#define RX_FIFO_WIDTH_MSK GENMASK(29, 24)
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#define RX_FIFO_WIDTH_SHFT 24
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#define RX_FIFO_DEPTH_MSK GENMASK(21, 16)
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#define RX_FIFO_DEPTH_SHFT 16
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#define HW_VER_MAJOR_MASK GENMASK(31, 28)
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#define HW_VER_MAJOR_SHFT 28
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#define HW_VER_MINOR_MASK GENMASK(27, 16)
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#define HW_VER_MINOR_SHFT 16
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#define HW_VER_STEP_MASK GENMASK(15, 0)
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#define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT)
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#define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
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#define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
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/* QUP SE VERSION value for major number 2 and minor number 5 */
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#define QUP_SE_VERSION_2_5 0x20050000
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/*
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* Define bandwidth thresholds that cause the underlying Core 2X interconnect
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* clock to run at the named frequency. These baseline values are recommended
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* by the hardware team, and are not dynamically scaled with GENI bandwidth
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* beyond basic on/off.
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*/
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#define CORE_2X_19_2_MHZ 960
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#define CORE_2X_50_MHZ 2500
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#define CORE_2X_100_MHZ 5000
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#define CORE_2X_150_MHZ 7500
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#define CORE_2X_200_MHZ 10000
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#define CORE_2X_236_MHZ 16383
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#define GENI_DEFAULT_BW Bps_to_icc(1000)
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#if IS_ENABLED(CONFIG_QCOM_GENI_SE)
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u32 geni_se_get_qup_hw_version(struct geni_se *se);
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/**
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* geni_se_read_proto() - Read the protocol configured for a serial engine
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* @se: Pointer to the concerned serial engine.
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*
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* Return: Protocol value as configured in the serial engine.
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*/
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static inline u32 geni_se_read_proto(struct geni_se *se)
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{
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u32 val;
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val = readl_relaxed(se->base + GENI_FW_REVISION_RO);
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return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT;
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}
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/**
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* geni_se_setup_m_cmd() - Setup the primary sequencer
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* @se: Pointer to the concerned serial engine.
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* @cmd: Command/Operation to setup in the primary sequencer.
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* @params: Parameter for the sequencer command.
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*
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* This function is used to configure the primary sequencer with the
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* command and its associated parameters.
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*/
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static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params)
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{
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u32 m_cmd;
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m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK);
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writel(m_cmd, se->base + SE_GENI_M_CMD0);
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}
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/**
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* geni_se_setup_s_cmd() - Setup the secondary sequencer
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* @se: Pointer to the concerned serial engine.
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* @cmd: Command/Operation to setup in the secondary sequencer.
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* @params: Parameter for the sequencer command.
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*
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* This function is used to configure the secondary sequencer with the
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* command and its associated parameters.
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*/
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static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params)
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{
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u32 s_cmd;
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s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0);
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s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK);
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s_cmd |= (cmd << S_OPCODE_SHFT);
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s_cmd |= (params & S_PARAMS_MSK);
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writel(s_cmd, se->base + SE_GENI_S_CMD0);
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}
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/**
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* geni_se_cancel_m_cmd() - Cancel the command configured in the primary
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* sequencer
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* @se: Pointer to the concerned serial engine.
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*
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* This function is used to cancel the currently configured command in the
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* primary sequencer.
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*/
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static inline void geni_se_cancel_m_cmd(struct geni_se *se)
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{
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writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG);
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}
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/**
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* geni_se_cancel_s_cmd() - Cancel the command configured in the secondary
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* sequencer
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* @se: Pointer to the concerned serial engine.
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*
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* This function is used to cancel the currently configured command in the
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* secondary sequencer.
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*/
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static inline void geni_se_cancel_s_cmd(struct geni_se *se)
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{
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writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG);
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}
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/**
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* geni_se_abort_m_cmd() - Abort the command configured in the primary sequencer
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* @se: Pointer to the concerned serial engine.
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*
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* This function is used to force abort the currently configured command in the
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* primary sequencer.
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*/
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static inline void geni_se_abort_m_cmd(struct geni_se *se)
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{
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writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG);
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}
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/**
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* geni_se_abort_s_cmd() - Abort the command configured in the secondary
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* sequencer
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* @se: Pointer to the concerned serial engine.
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*
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* This function is used to force abort the currently configured command in the
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* secondary sequencer.
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*/
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static inline void geni_se_abort_s_cmd(struct geni_se *se)
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{
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writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG);
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}
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/**
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* geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine
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* @se: Pointer to the concerned serial engine.
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*
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* This function is used to get the depth i.e. number of elements in the
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* TX fifo of the serial engine.
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*
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* Return: TX fifo depth in units of FIFO words.
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*/
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static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se)
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{
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u32 val;
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val = readl_relaxed(se->base + SE_HW_PARAM_0);
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return (val & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT;
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}
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/**
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* geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine
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* @se: Pointer to the concerned serial engine.
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*
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* This function is used to get the width i.e. word size per element in the
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* TX fifo of the serial engine.
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*
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* Return: TX fifo width in bits
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*/
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static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se)
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{
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u32 val;
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val = readl_relaxed(se->base + SE_HW_PARAM_0);
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return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT;
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}
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/**
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* geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine
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* @se: Pointer to the concerned serial engine.
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*
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* This function is used to get the depth i.e. number of elements in the
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* RX fifo of the serial engine.
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*
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* Return: RX fifo depth in units of FIFO words
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*/
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static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se)
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{
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u32 val;
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val = readl_relaxed(se->base + SE_HW_PARAM_1);
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return (val & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT;
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}
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void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr);
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void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode);
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void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
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bool msb_to_lsb, bool tx_cfg, bool rx_cfg);
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int geni_se_resources_off(struct geni_se *se);
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int geni_se_resources_on(struct geni_se *se);
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int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl);
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int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
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unsigned int *index, unsigned long *res_freq,
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bool exact);
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int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
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dma_addr_t *iova);
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int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
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dma_addr_t *iova);
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void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
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void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
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int geni_icc_get(struct geni_se *se, const char *icc_ddr);
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int geni_icc_set_bw(struct geni_se *se);
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void geni_icc_set_tag(struct geni_se *se, u32 tag);
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int geni_icc_enable(struct geni_se *se);
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int geni_icc_disable(struct geni_se *se);
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#endif
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#endif
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