385 lines
8.9 KiB
C
385 lines
8.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
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/* core clocks */
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#define PLL_APLLB 1
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#define PLL_APLLL 2
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#define PLL_DPLL 3
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#define PLL_CPLL 4
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#define PLL_GPLL 5
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#define PLL_NPLL 6
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#define ARMCLKB 7
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#define ARMCLKL 8
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/* sclk gates (special clocks) */
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#define SCLK_GPU_CORE 64
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#define SCLK_SPI0 65
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#define SCLK_SPI1 66
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#define SCLK_SPI2 67
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#define SCLK_SDMMC 68
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#define SCLK_SDIO0 69
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#define SCLK_EMMC 71
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#define SCLK_TSADC 72
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#define SCLK_SARADC 73
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#define SCLK_NANDC0 75
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#define SCLK_UART0 77
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#define SCLK_UART1 78
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#define SCLK_UART2 79
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#define SCLK_UART3 80
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#define SCLK_UART4 81
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#define SCLK_I2S_8CH 82
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#define SCLK_SPDIF_8CH 83
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#define SCLK_I2S_2CH 84
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#define SCLK_TIMER00 85
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#define SCLK_TIMER01 86
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#define SCLK_TIMER02 87
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#define SCLK_TIMER03 88
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#define SCLK_TIMER04 89
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#define SCLK_TIMER05 90
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#define SCLK_OTGPHY0 93
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#define SCLK_OTG_ADP 96
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#define SCLK_HSICPHY480M 97
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#define SCLK_HSICPHY12M 98
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#define SCLK_MACREF 99
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#define SCLK_VOP0_PWM 100
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#define SCLK_MAC_RX 102
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#define SCLK_MAC_TX 103
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#define SCLK_EDP_24M 104
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#define SCLK_EDP 105
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#define SCLK_RGA 106
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#define SCLK_ISP 107
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#define SCLK_HDCP 108
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#define SCLK_HDMI_HDCP 109
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#define SCLK_HDMI_CEC 110
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#define SCLK_HEVC_CABAC 111
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#define SCLK_HEVC_CORE 112
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#define SCLK_I2S_8CH_OUT 113
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#define SCLK_SDMMC_DRV 114
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#define SCLK_SDIO0_DRV 115
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#define SCLK_EMMC_DRV 117
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#define SCLK_SDMMC_SAMPLE 118
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#define SCLK_SDIO0_SAMPLE 119
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#define SCLK_EMMC_SAMPLE 121
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#define SCLK_USBPHY480M 122
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#define SCLK_PVTM_CORE 123
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#define SCLK_PVTM_GPU 124
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#define SCLK_PVTM_PMU 125
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#define SCLK_SFC 126
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#define SCLK_MAC 127
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#define SCLK_MACREF_OUT 128
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#define SCLK_TIMER10 133
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#define SCLK_TIMER11 134
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#define SCLK_TIMER12 135
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#define SCLK_TIMER13 136
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#define SCLK_TIMER14 137
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#define SCLK_TIMER15 138
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#define SCLK_VIP_OUT 139
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#define DCLK_VOP 190
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#define MCLK_CRYPTO 191
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/* aclk gates */
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#define ACLK_GPU_MEM 192
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#define ACLK_GPU_CFG 193
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#define ACLK_DMAC_BUS 194
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#define ACLK_DMAC_PERI 195
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#define ACLK_PERI_MMU 196
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#define ACLK_GMAC 197
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#define ACLK_VOP 198
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#define ACLK_VOP_IEP 199
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#define ACLK_RGA 200
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#define ACLK_HDCP 201
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#define ACLK_IEP 202
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#define ACLK_VIO0_NOC 203
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#define ACLK_VIP 204
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#define ACLK_ISP 205
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#define ACLK_VIO1_NOC 206
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#define ACLK_VIDEO 208
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#define ACLK_BUS 209
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#define ACLK_PERI 210
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/* pclk gates */
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#define PCLK_GPIO0 320
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#define PCLK_GPIO1 321
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#define PCLK_GPIO2 322
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#define PCLK_GPIO3 323
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#define PCLK_PMUGRF 324
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#define PCLK_MAILBOX 325
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#define PCLK_GRF 329
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#define PCLK_SGRF 330
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#define PCLK_PMU 331
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#define PCLK_I2C0 332
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#define PCLK_I2C1 333
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#define PCLK_I2C2 334
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#define PCLK_I2C3 335
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#define PCLK_I2C4 336
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#define PCLK_I2C5 337
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#define PCLK_SPI0 338
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#define PCLK_SPI1 339
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#define PCLK_SPI2 340
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#define PCLK_UART0 341
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#define PCLK_UART1 342
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#define PCLK_UART2 343
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#define PCLK_UART3 344
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#define PCLK_UART4 345
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#define PCLK_TSADC 346
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#define PCLK_SARADC 347
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#define PCLK_SIM 348
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#define PCLK_GMAC 349
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#define PCLK_PWM0 350
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#define PCLK_PWM1 351
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#define PCLK_TIMER0 353
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#define PCLK_TIMER1 354
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#define PCLK_EDP_CTRL 355
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#define PCLK_MIPI_DSI0 356
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#define PCLK_MIPI_CSI 358
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#define PCLK_HDCP 359
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#define PCLK_HDMI_CTRL 360
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#define PCLK_VIO_H2P 361
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#define PCLK_BUS 362
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#define PCLK_PERI 363
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#define PCLK_DDRUPCTL 364
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#define PCLK_DDRPHY 365
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#define PCLK_ISP 366
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#define PCLK_VIP 367
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#define PCLK_WDT 368
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#define PCLK_EFUSE256 369
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#define PCLK_DPHYRX 370
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#define PCLK_DPHYTX0 371
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/* hclk gates */
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#define HCLK_SFC 448
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#define HCLK_OTG0 449
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#define HCLK_HOST0 450
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#define HCLK_HOST1 451
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#define HCLK_HSIC 452
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#define HCLK_NANDC0 453
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#define HCLK_TSP 455
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#define HCLK_SDMMC 456
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#define HCLK_SDIO0 457
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#define HCLK_EMMC 459
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#define HCLK_HSADC 460
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#define HCLK_CRYPTO 461
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#define HCLK_I2S_2CH 462
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#define HCLK_I2S_8CH 463
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#define HCLK_SPDIF 464
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#define HCLK_VOP 465
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#define HCLK_ROM 467
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#define HCLK_IEP 468
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#define HCLK_ISP 469
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#define HCLK_RGA 470
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#define HCLK_VIO_AHB_ARBI 471
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#define HCLK_VIO_NOC 472
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#define HCLK_VIP 473
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#define HCLK_VIO_H2P 474
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#define HCLK_VIO_HDCPMMU 475
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#define HCLK_VIDEO 476
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#define HCLK_BUS 477
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#define HCLK_PERI 478
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#define CLK_NR_CLKS (HCLK_PERI + 1)
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/* soft-reset indices */
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#define SRST_CORE_B0 0
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#define SRST_CORE_B1 1
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#define SRST_CORE_B2 2
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#define SRST_CORE_B3 3
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#define SRST_CORE_B0_PO 4
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#define SRST_CORE_B1_PO 5
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#define SRST_CORE_B2_PO 6
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#define SRST_CORE_B3_PO 7
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#define SRST_L2_B 8
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#define SRST_ADB_B 9
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#define SRST_PD_CORE_B_NIU 10
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#define SRST_PDBUS_STRSYS 11
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#define SRST_SOCDBG_B 14
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#define SRST_CORE_B_DBG 15
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#define SRST_DMAC1 18
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#define SRST_INTMEM 19
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#define SRST_ROM 20
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#define SRST_SPDIF8CH 21
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#define SRST_I2S8CH 23
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#define SRST_MAILBOX 24
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#define SRST_I2S2CH 25
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#define SRST_EFUSE_256 26
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#define SRST_MCU_SYS 28
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#define SRST_MCU_PO 29
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#define SRST_MCU_NOC 30
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#define SRST_EFUSE 31
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#define SRST_GPIO0 32
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#define SRST_GPIO1 33
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#define SRST_GPIO2 34
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#define SRST_GPIO3 35
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#define SRST_GPIO4 36
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#define SRST_PMUGRF 41
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#define SRST_I2C0 42
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#define SRST_I2C1 43
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#define SRST_I2C2 44
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#define SRST_I2C3 45
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#define SRST_I2C4 46
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#define SRST_I2C5 47
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#define SRST_DWPWM 48
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#define SRST_MMC_PERI 49
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#define SRST_PERIPH_MMU 50
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#define SRST_GRF 55
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#define SRST_PMU 56
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#define SRST_PERIPH_AXI 57
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#define SRST_PERIPH_AHB 58
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#define SRST_PERIPH_APB 59
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#define SRST_PERIPH_NIU 60
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#define SRST_PDPERI_AHB_ARBI 61
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#define SRST_EMEM 62
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#define SRST_USB_PERI 63
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#define SRST_DMAC2 64
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#define SRST_MAC 66
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#define SRST_GPS 67
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#define SRST_RKPWM 69
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#define SRST_USBHOST0 72
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#define SRST_HSIC 73
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#define SRST_HSIC_AUX 74
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#define SRST_HSIC_PHY 75
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#define SRST_HSADC 76
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#define SRST_NANDC0 77
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#define SRST_SFC 79
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#define SRST_SPI0 83
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#define SRST_SPI1 84
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#define SRST_SPI2 85
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#define SRST_SARADC 87
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#define SRST_PDALIVE_NIU 88
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#define SRST_PDPMU_INTMEM 89
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#define SRST_PDPMU_NIU 90
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#define SRST_SGRF 91
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#define SRST_VIO_ARBI 96
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#define SRST_RGA_NIU 97
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#define SRST_VIO0_NIU_AXI 98
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#define SRST_VIO_NIU_AHB 99
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#define SRST_LCDC0_AXI 100
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#define SRST_LCDC0_AHB 101
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#define SRST_LCDC0_DCLK 102
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#define SRST_VIP 104
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#define SRST_RGA_CORE 105
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#define SRST_IEP_AXI 106
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#define SRST_IEP_AHB 107
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#define SRST_RGA_AXI 108
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#define SRST_RGA_AHB 109
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#define SRST_ISP 110
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#define SRST_EDP_24M 111
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#define SRST_VIDEO_AXI 112
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#define SRST_VIDEO_AHB 113
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#define SRST_MIPIDPHYTX 114
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#define SRST_MIPIDSI0 115
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#define SRST_MIPIDPHYRX 116
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#define SRST_MIPICSI 117
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#define SRST_GPU 120
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#define SRST_HDMI 121
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#define SRST_EDP 122
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#define SRST_PMU_PVTM 123
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#define SRST_CORE_PVTM 124
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#define SRST_GPU_PVTM 125
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#define SRST_GPU_SYS 126
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#define SRST_GPU_MEM_NIU 127
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#define SRST_MMC0 128
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#define SRST_SDIO0 129
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#define SRST_EMMC 131
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#define SRST_USBOTG_AHB 132
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#define SRST_USBOTG_PHY 133
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#define SRST_USBOTG_CON 134
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#define SRST_USBHOST0_AHB 135
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#define SRST_USBHOST0_PHY 136
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#define SRST_USBHOST0_CON 137
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#define SRST_USBOTG_UTMI 138
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#define SRST_USBHOST1_UTMI 139
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#define SRST_USB_ADP 141
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#define SRST_CORESIGHT 144
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#define SRST_PD_CORE_AHB_NOC 145
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#define SRST_PD_CORE_APB_NOC 146
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#define SRST_GIC 148
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#define SRST_LCDC_PWM0 149
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#define SRST_RGA_H2P_BRG 153
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#define SRST_VIDEO 154
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#define SRST_GPU_CFG_NIU 157
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#define SRST_TSADC 159
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#define SRST_DDRPHY0 160
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#define SRST_DDRPHY0_APB 161
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#define SRST_DDRCTRL0 162
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#define SRST_DDRCTRL0_APB 163
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#define SRST_VIDEO_NIU 165
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#define SRST_VIDEO_NIU_AHB 167
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#define SRST_DDRMSCH0 170
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#define SRST_PDBUS_AHB 173
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#define SRST_CRYPTO 174
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#define SRST_UART0 179
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#define SRST_UART1 180
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#define SRST_UART2 181
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#define SRST_UART3 182
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#define SRST_UART4 183
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#define SRST_SIMC 186
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#define SRST_TSP 188
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#define SRST_TSP_CLKIN0 189
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#define SRST_CORE_L0 192
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#define SRST_CORE_L1 193
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#define SRST_CORE_L2 194
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#define SRST_CORE_L3 195
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#define SRST_CORE_L0_PO 195
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#define SRST_CORE_L1_PO 197
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#define SRST_CORE_L2_PO 198
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#define SRST_CORE_L3_PO 199
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#define SRST_L2_L 200
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#define SRST_ADB_L 201
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#define SRST_PD_CORE_L_NIU 202
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#define SRST_CCI_SYS 203
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#define SRST_CCI_DDR 204
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#define SRST_CCI 205
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#define SRST_SOCDBG_L 206
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#define SRST_CORE_L_DBG 207
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#define SRST_CORE_B0_NC 208
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#define SRST_CORE_B0_PO_NC 209
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#define SRST_L2_B_NC 210
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#define SRST_ADB_B_NC 211
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#define SRST_PD_CORE_B_NIU_NC 212
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#define SRST_PDBUS_STRSYS_NC 213
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#define SRST_CORE_L0_NC 214
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#define SRST_CORE_L0_PO_NC 215
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#define SRST_L2_L_NC 216
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#define SRST_ADB_L_NC 217
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#define SRST_PD_CORE_L_NIU_NC 218
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#define SRST_CCI_SYS_NC 219
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#define SRST_CCI_DDR_NC 220
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#define SRST_CCI_NC 221
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#define SRST_TRACE_NC 222
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#define SRST_TIMER00 224
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#define SRST_TIMER01 225
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#define SRST_TIMER02 226
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#define SRST_TIMER03 227
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#define SRST_TIMER04 228
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#define SRST_TIMER05 229
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#define SRST_TIMER10 230
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#define SRST_TIMER11 231
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#define SRST_TIMER12 232
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#define SRST_TIMER13 233
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#define SRST_TIMER14 234
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#define SRST_TIMER15 235
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#define SRST_TIMER0_APB 236
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#define SRST_TIMER1_APB 237
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#endif
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