183 lines
5.4 KiB
C
183 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2015 MediaTek Inc.
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* Author:
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* Zhigang.Wei <zhigang.wei@mediatek.com>
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* Chunfeng.Yun <chunfeng.yun@mediatek.com>
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*/
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#ifndef _XHCI_MTK_H_
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#define _XHCI_MTK_H_
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#include <linux/clk.h>
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#include <linux/hashtable.h>
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#include "xhci.h"
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#define BULK_CLKS_NUM 5
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/* support at most 64 ep, use 32 size hash table */
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#define SCH_EP_HASH_BITS 5
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/**
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* To simplify scheduler algorithm, set a upper limit for ESIT,
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* if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
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* round down to the limit value, that means allocating more
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* bandwidth to it.
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*/
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#define XHCI_MTK_MAX_ESIT (1 << 6)
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#define XHCI_MTK_BW_INDEX(x) ((x) & (XHCI_MTK_MAX_ESIT - 1))
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/**
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* @fs_bus_bw: array to keep track of bandwidth already used for FS
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* @ep_list: Endpoints using this TT
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*/
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struct mu3h_sch_tt {
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u32 fs_bus_bw[XHCI_MTK_MAX_ESIT];
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struct list_head ep_list;
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};
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/**
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* struct mu3h_sch_bw_info: schedule information for bandwidth domain
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*
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* @bus_bw: array to keep track of bandwidth already used at each uframes
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*
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* treat a HS root port as a bandwidth domain, but treat a SS root port as
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* two bandwidth domains, one for IN eps and another for OUT eps.
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*/
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struct mu3h_sch_bw_info {
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u32 bus_bw[XHCI_MTK_MAX_ESIT];
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};
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/**
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* struct mu3h_sch_ep_info: schedule information for endpoint
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*
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* @esit: unit is 125us, equal to 2 << Interval field in ep-context
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* @num_esit: number of @esit in a period
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* @num_budget_microframes: number of continuous uframes
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* (@repeat==1) scheduled within the interval
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* @bw_cost_per_microframe: bandwidth cost per microframe
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* @hentry: hash table entry
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* @endpoint: linked into bandwidth domain which it belongs to
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* @tt_endpoint: linked into mu3h_sch_tt's list which it belongs to
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* @bw_info: bandwidth domain which this endpoint belongs
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* @sch_tt: mu3h_sch_tt linked into
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* @ep_type: endpoint type
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* @maxpkt: max packet size of endpoint
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* @ep: address of usb_host_endpoint struct
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* @allocated: the bandwidth is aready allocated from bus_bw
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* @offset: which uframe of the interval that transfer should be
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* scheduled first time within the interval
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* @repeat: the time gap between two uframes that transfers are
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* scheduled within a interval. in the simple algorithm, only
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* assign 0 or 1 to it; 0 means using only one uframe in a
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* interval, and 1 means using @num_budget_microframes
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* continuous uframes
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* @pkts: number of packets to be transferred in the scheduled uframes
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* @cs_count: number of CS that host will trigger
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* @burst_mode: burst mode for scheduling. 0: normal burst mode,
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* distribute the bMaxBurst+1 packets for a single burst
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* according to @pkts and @repeat, repeate the burst multiple
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* times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
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* according to @pkts and @repeat. normal mode is used by
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* default
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* @bw_budget_table: table to record bandwidth budget per microframe
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*/
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struct mu3h_sch_ep_info {
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u32 esit;
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u32 num_esit;
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u32 num_budget_microframes;
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u32 bw_cost_per_microframe;
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struct list_head endpoint;
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struct hlist_node hentry;
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struct list_head tt_endpoint;
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struct mu3h_sch_bw_info *bw_info;
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struct mu3h_sch_tt *sch_tt;
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u32 ep_type;
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u32 maxpkt;
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struct usb_host_endpoint *ep;
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enum usb_device_speed speed;
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bool allocated;
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/*
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* mtk xHCI scheduling information put into reserved DWs
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* in ep context
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*/
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u32 offset;
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u32 repeat;
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u32 pkts;
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u32 cs_count;
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u32 burst_mode;
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u32 bw_budget_table[];
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};
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#define MU3C_U3_PORT_MAX 4
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#define MU3C_U2_PORT_MAX 5
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/**
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* struct mu3c_ippc_regs: MTK ssusb ip port control registers
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* @ip_pw_ctr0~3: ip power and clock control registers
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* @ip_pw_sts1~2: ip power and clock status registers
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* @ip_xhci_cap: ip xHCI capability register
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* @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
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* @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
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* @u2_phy_pll: usb2 phy pll control register
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*/
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struct mu3c_ippc_regs {
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__le32 ip_pw_ctr0;
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__le32 ip_pw_ctr1;
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__le32 ip_pw_ctr2;
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__le32 ip_pw_ctr3;
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__le32 ip_pw_sts1;
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__le32 ip_pw_sts2;
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__le32 reserved0[3];
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__le32 ip_xhci_cap;
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__le32 reserved1[2];
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__le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
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__le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
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__le32 reserved2;
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__le32 u2_phy_pll;
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__le32 reserved3[33]; /* 0x80 ~ 0xff */
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};
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struct xhci_hcd_mtk {
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struct device *dev;
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struct usb_hcd *hcd;
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struct mu3h_sch_bw_info *sch_array;
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struct list_head bw_ep_chk_list;
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DECLARE_HASHTABLE(sch_ep_hash, SCH_EP_HASH_BITS);
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struct mu3c_ippc_regs __iomem *ippc_regs;
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int num_u2_ports;
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int num_u3_ports;
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int u2p_dis_msk;
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int u3p_dis_msk;
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struct regulator *vusb33;
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struct regulator *vbus;
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struct clk_bulk_data clks[BULK_CLKS_NUM];
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unsigned int has_ippc:1;
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unsigned int lpm_support:1;
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unsigned int u2_lpm_disable:1;
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/* usb remote wakeup */
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unsigned int uwk_en:1;
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struct regmap *uwk;
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u32 uwk_reg_base;
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u32 uwk_vers;
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/* quirk */
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u32 rxfifo_depth;
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};
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static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
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{
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return dev_get_drvdata(hcd->self.controller);
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}
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int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
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void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
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int xhci_mtk_add_ep(struct usb_hcd *hcd, struct usb_device *udev,
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struct usb_host_endpoint *ep);
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int xhci_mtk_drop_ep(struct usb_hcd *hcd, struct usb_device *udev,
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struct usb_host_endpoint *ep);
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int xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
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void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
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#endif /* _XHCI_MTK_H_ */
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