835 lines
21 KiB
C
835 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* TI DaVinci DM355 chip specific setup
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*
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* Author: Kevin Hilman, Deep Root Systems, LLC
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*
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* 2007 (c) Deep Root Systems, LLC.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk/davinci.h>
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#include <linux/clkdev.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irqchip/irq-davinci-aintc.h>
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#include <linux/platform_data/edma.h>
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#include <linux/platform_data/gpio-davinci.h>
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#include <linux/platform_data/spi-davinci.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/spi/spi.h>
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#include <asm/mach/map.h>
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#include <mach/common.h>
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#include <mach/cputype.h>
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#include <mach/mux.h>
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#include <mach/serial.h>
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#include <clocksource/timer-davinci.h>
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#include "asp.h"
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#include "davinci.h"
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#include "irqs.h"
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#include "mux.h"
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#define DM355_UART2_BASE (IO_PHYS + 0x206000)
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#define DM355_OSD_BASE (IO_PHYS + 0x70200)
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#define DM355_VENC_BASE (IO_PHYS + 0x70400)
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/*
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* Device specific clocks
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*/
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#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
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static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
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static struct resource dm355_spi0_resources[] = {
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{
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.start = 0x01c66000,
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.end = 0x01c667ff,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = DAVINCI_INTC_IRQ(IRQ_DM355_SPINT0_0),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct davinci_spi_platform_data dm355_spi0_pdata = {
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.version = SPI_VERSION_1,
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.num_chipselect = 2,
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.cshold_bug = true,
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.dma_event_q = EVENTQ_1,
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.prescaler_limit = 1,
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};
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static struct platform_device dm355_spi0_device = {
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.name = "spi_davinci",
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.id = 0,
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.dev = {
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.dma_mask = &dm355_spi0_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &dm355_spi0_pdata,
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},
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.num_resources = ARRAY_SIZE(dm355_spi0_resources),
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.resource = dm355_spi0_resources,
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};
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void __init dm355_init_spi0(unsigned chipselect_mask,
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const struct spi_board_info *info, unsigned len)
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{
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/* for now, assume we need MISO */
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davinci_cfg_reg(DM355_SPI0_SDI);
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/* not all slaves will be wired up */
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if (chipselect_mask & BIT(0))
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davinci_cfg_reg(DM355_SPI0_SDENA0);
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if (chipselect_mask & BIT(1))
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davinci_cfg_reg(DM355_SPI0_SDENA1);
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spi_register_board_info(info, len);
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platform_device_register(&dm355_spi0_device);
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}
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/*----------------------------------------------------------------------*/
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#define INTMUX 0x18
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#define EVTMUX 0x1c
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/*
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* Device specific mux setup
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*
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* soc description mux mode mode mux dbg
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* reg offset mask mode
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*/
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static const struct mux_config dm355_pins[] = {
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#ifdef CONFIG_DAVINCI_MUX
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MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
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MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
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MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
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MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
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MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
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MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
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MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
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MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
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MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
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MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
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MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
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MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
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MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
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MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
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MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
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MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
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MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
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MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
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INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
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INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
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INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
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EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
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EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
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EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
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MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false)
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MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false)
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MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false)
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MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
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MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
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MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false)
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MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false)
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MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false)
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MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false)
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MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false)
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MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
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MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false)
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#endif
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};
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static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
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[IRQ_DM355_CCDC_VDINT0] = 2,
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[IRQ_DM355_CCDC_VDINT1] = 6,
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[IRQ_DM355_CCDC_VDINT2] = 6,
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[IRQ_DM355_IPIPE_HST] = 6,
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[IRQ_DM355_H3AINT] = 6,
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[IRQ_DM355_IPIPE_SDR] = 6,
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[IRQ_DM355_IPIPEIFINT] = 6,
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[IRQ_DM355_OSDINT] = 7,
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[IRQ_DM355_VENCINT] = 6,
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[IRQ_ASQINT] = 6,
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[IRQ_IMXINT] = 6,
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[IRQ_USBINT] = 4,
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[IRQ_DM355_RTOINT] = 4,
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[IRQ_DM355_UARTINT2] = 7,
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[IRQ_DM355_TINT6] = 7,
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[IRQ_CCINT0] = 5, /* dma */
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[IRQ_CCERRINT] = 5, /* dma */
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[IRQ_TCERRINT0] = 5, /* dma */
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[IRQ_TCERRINT] = 5, /* dma */
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[IRQ_DM355_SPINT2_1] = 7,
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[IRQ_DM355_TINT7] = 4,
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[IRQ_DM355_SDIOINT0] = 7,
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[IRQ_MBXINT] = 7,
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[IRQ_MBRINT] = 7,
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[IRQ_MMCINT] = 7,
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[IRQ_DM355_MMCINT1] = 7,
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[IRQ_DM355_PWMINT3] = 7,
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[IRQ_DDRINT] = 7,
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[IRQ_AEMIFINT] = 7,
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[IRQ_DM355_SDIOINT1] = 4,
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[IRQ_TINT0_TINT12] = 2, /* clockevent */
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[IRQ_TINT0_TINT34] = 2, /* clocksource */
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[IRQ_TINT1_TINT12] = 7, /* DSP timer */
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[IRQ_TINT1_TINT34] = 7, /* system tick */
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[IRQ_PWMINT0] = 7,
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[IRQ_PWMINT1] = 7,
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[IRQ_PWMINT2] = 7,
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[IRQ_I2C] = 3,
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[IRQ_UARTINT0] = 3,
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[IRQ_UARTINT1] = 3,
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[IRQ_DM355_SPINT0_0] = 3,
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[IRQ_DM355_SPINT0_1] = 3,
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[IRQ_DM355_GPIO0] = 3,
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[IRQ_DM355_GPIO1] = 7,
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[IRQ_DM355_GPIO2] = 4,
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[IRQ_DM355_GPIO3] = 4,
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[IRQ_DM355_GPIO4] = 7,
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[IRQ_DM355_GPIO5] = 7,
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[IRQ_DM355_GPIO6] = 7,
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[IRQ_DM355_GPIO7] = 7,
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[IRQ_DM355_GPIO8] = 7,
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[IRQ_DM355_GPIO9] = 7,
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[IRQ_DM355_GPIOBNK0] = 7,
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[IRQ_DM355_GPIOBNK1] = 7,
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[IRQ_DM355_GPIOBNK2] = 7,
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[IRQ_DM355_GPIOBNK3] = 7,
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[IRQ_DM355_GPIOBNK4] = 7,
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[IRQ_DM355_GPIOBNK5] = 7,
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[IRQ_DM355_GPIOBNK6] = 7,
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[IRQ_COMMTX] = 7,
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[IRQ_COMMRX] = 7,
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[IRQ_EMUINT] = 7,
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};
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/*----------------------------------------------------------------------*/
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static s8 queue_priority_mapping[][2] = {
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/* {event queue no, Priority} */
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{0, 3},
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{1, 7},
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{-1, -1},
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};
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static const struct dma_slave_map dm355_edma_map[] = {
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{ "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
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{ "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
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{ "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) },
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{ "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) },
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{ "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
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{ "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
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{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
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{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
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{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
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{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
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{ "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
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{ "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
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{ "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
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{ "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
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};
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static struct edma_soc_info dm355_edma_pdata = {
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.queue_priority_mapping = queue_priority_mapping,
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.default_queue = EVENTQ_1,
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.slave_map = dm355_edma_map,
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.slavecnt = ARRAY_SIZE(dm355_edma_map),
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};
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static struct resource edma_resources[] = {
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{
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.name = "edma3_cc",
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.start = 0x01c00000,
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.end = 0x01c00000 + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma3_tc0",
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.start = 0x01c10000,
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.end = 0x01c10000 + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma3_tc1",
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.start = 0x01c10400,
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.end = 0x01c10400 + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma3_ccint",
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.start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "edma3_ccerrint",
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.start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
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.flags = IORESOURCE_IRQ,
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},
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/* not using (or muxing) TC*_ERR */
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};
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static const struct platform_device_info dm355_edma_device __initconst = {
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.name = "edma",
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.id = 0,
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.dma_mask = DMA_BIT_MASK(32),
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.res = edma_resources,
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.num_res = ARRAY_SIZE(edma_resources),
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.data = &dm355_edma_pdata,
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.size_data = sizeof(dm355_edma_pdata),
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};
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static struct resource dm355_asp1_resources[] = {
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{
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.name = "mpu",
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.start = DAVINCI_ASP1_BASE,
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.end = DAVINCI_ASP1_BASE + SZ_8K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = DAVINCI_DMA_ASP1_TX,
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.end = DAVINCI_DMA_ASP1_TX,
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.flags = IORESOURCE_DMA,
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},
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{
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.start = DAVINCI_DMA_ASP1_RX,
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.end = DAVINCI_DMA_ASP1_RX,
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.flags = IORESOURCE_DMA,
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},
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};
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static struct platform_device dm355_asp1_device = {
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.name = "davinci-mcbsp",
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.id = 1,
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.num_resources = ARRAY_SIZE(dm355_asp1_resources),
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.resource = dm355_asp1_resources,
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};
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static void dm355_ccdc_setup_pinmux(void)
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{
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davinci_cfg_reg(DM355_VIN_PCLK);
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davinci_cfg_reg(DM355_VIN_CAM_WEN);
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davinci_cfg_reg(DM355_VIN_CAM_VD);
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davinci_cfg_reg(DM355_VIN_CAM_HD);
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davinci_cfg_reg(DM355_VIN_YIN_EN);
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davinci_cfg_reg(DM355_VIN_CINL_EN);
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davinci_cfg_reg(DM355_VIN_CINH_EN);
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}
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static struct resource dm355_vpss_resources[] = {
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{
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/* VPSS BL Base address */
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.name = "vpss",
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.start = 0x01c70800,
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.end = 0x01c70800 + 0xff,
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.flags = IORESOURCE_MEM,
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},
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{
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/* VPSS CLK Base address */
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.name = "vpss",
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.start = 0x01c70000,
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.end = 0x01c70000 + 0xf,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device dm355_vpss_device = {
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.name = "vpss",
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.id = -1,
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.dev.platform_data = "dm355_vpss",
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.num_resources = ARRAY_SIZE(dm355_vpss_resources),
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.resource = dm355_vpss_resources,
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};
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static struct resource vpfe_resources[] = {
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{
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.start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
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.end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
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.end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
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static struct resource dm355_ccdc_resource[] = {
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/* CCDC Base address */
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{
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.flags = IORESOURCE_MEM,
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.start = 0x01c70600,
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.end = 0x01c70600 + 0x1ff,
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},
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};
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static struct platform_device dm355_ccdc_dev = {
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.name = "dm355_ccdc",
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.id = -1,
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.num_resources = ARRAY_SIZE(dm355_ccdc_resource),
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.resource = dm355_ccdc_resource,
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.dev = {
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.dma_mask = &vpfe_capture_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = dm355_ccdc_setup_pinmux,
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},
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};
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static struct platform_device vpfe_capture_dev = {
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.name = CAPTURE_DRV_NAME,
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.id = -1,
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.num_resources = ARRAY_SIZE(vpfe_resources),
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.resource = vpfe_resources,
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.dev = {
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.dma_mask = &vpfe_capture_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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static struct resource dm355_osd_resources[] = {
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{
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.start = DM355_OSD_BASE,
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.end = DM355_OSD_BASE + 0x17f,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device dm355_osd_dev = {
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.name = DM355_VPBE_OSD_SUBDEV_NAME,
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.id = -1,
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.num_resources = ARRAY_SIZE(dm355_osd_resources),
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.resource = dm355_osd_resources,
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.dev = {
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.dma_mask = &vpfe_capture_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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static struct resource dm355_venc_resources[] = {
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{
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.start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
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.end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
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.flags = IORESOURCE_IRQ,
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},
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/* venc registers io space */
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{
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.start = DM355_VENC_BASE,
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.end = DM355_VENC_BASE + 0x17f,
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.flags = IORESOURCE_MEM,
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},
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/* VDAC config register io space */
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{
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.start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
|
|
.end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct resource dm355_v4l2_disp_resources[] = {
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
/* venc registers io space */
|
|
{
|
|
.start = DM355_VENC_BASE,
|
|
.end = DM355_VENC_BASE + 0x17f,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static int dm355_vpbe_setup_pinmux(u32 if_type, int field)
|
|
{
|
|
switch (if_type) {
|
|
case MEDIA_BUS_FMT_SGRBG8_1X8:
|
|
davinci_cfg_reg(DM355_VOUT_FIELD_G70);
|
|
break;
|
|
case MEDIA_BUS_FMT_YUYV10_1X20:
|
|
if (field)
|
|
davinci_cfg_reg(DM355_VOUT_FIELD);
|
|
else
|
|
davinci_cfg_reg(DM355_VOUT_FIELD_G70);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
davinci_cfg_reg(DM355_VOUT_COUTL_EN);
|
|
davinci_cfg_reg(DM355_VOUT_COUTH_EN);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type,
|
|
unsigned int pclock)
|
|
{
|
|
void __iomem *vpss_clk_ctrl_reg;
|
|
|
|
vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
|
|
|
|
switch (type) {
|
|
case VPBE_ENC_STD:
|
|
writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE,
|
|
vpss_clk_ctrl_reg);
|
|
break;
|
|
case VPBE_ENC_DV_TIMINGS:
|
|
if (pclock > 27000000)
|
|
/*
|
|
* For HD, use external clock source since we cannot
|
|
* support HD mode with internal clocks.
|
|
*/
|
|
writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_device dm355_vpbe_display = {
|
|
.name = "vpbe-v4l2",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(dm355_v4l2_disp_resources),
|
|
.resource = dm355_v4l2_disp_resources,
|
|
.dev = {
|
|
.dma_mask = &vpfe_capture_dma_mask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
};
|
|
|
|
static struct venc_platform_data dm355_venc_pdata = {
|
|
.setup_pinmux = dm355_vpbe_setup_pinmux,
|
|
.setup_clock = dm355_venc_setup_clock,
|
|
};
|
|
|
|
static struct platform_device dm355_venc_dev = {
|
|
.name = DM355_VPBE_VENC_SUBDEV_NAME,
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(dm355_venc_resources),
|
|
.resource = dm355_venc_resources,
|
|
.dev = {
|
|
.dma_mask = &vpfe_capture_dma_mask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = (void *)&dm355_venc_pdata,
|
|
},
|
|
};
|
|
|
|
static struct platform_device dm355_vpbe_dev = {
|
|
.name = "vpbe_controller",
|
|
.id = -1,
|
|
.dev = {
|
|
.dma_mask = &vpfe_capture_dma_mask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
};
|
|
|
|
static struct resource dm355_gpio_resources[] = {
|
|
{ /* registers */
|
|
.start = DAVINCI_GPIO_BASE,
|
|
.end = DAVINCI_GPIO_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{ /* interrupt */
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
|
|
.no_auto_base = true,
|
|
.base = 0,
|
|
.ngpio = 104,
|
|
};
|
|
|
|
int __init dm355_gpio_register(void)
|
|
{
|
|
return davinci_gpio_register(dm355_gpio_resources,
|
|
ARRAY_SIZE(dm355_gpio_resources),
|
|
&dm355_gpio_platform_data);
|
|
}
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
static struct map_desc dm355_io_desc[] = {
|
|
{
|
|
.virtual = IO_VIRT,
|
|
.pfn = __phys_to_pfn(IO_PHYS),
|
|
.length = IO_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
};
|
|
|
|
/* Contents of JTAG ID register used to identify exact cpu type */
|
|
static struct davinci_id dm355_ids[] = {
|
|
{
|
|
.variant = 0x0,
|
|
.part_no = 0xb73b,
|
|
.manufacturer = 0x00f,
|
|
.cpu_id = DAVINCI_CPU_ID_DM355,
|
|
.name = "dm355",
|
|
},
|
|
};
|
|
|
|
/*
|
|
* Bottom half of timer0 is used for clockevent, top half is used for
|
|
* clocksource.
|
|
*/
|
|
static const struct davinci_timer_cfg dm355_timer_cfg = {
|
|
.reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
|
|
.irq = {
|
|
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
|
|
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
|
|
},
|
|
};
|
|
|
|
static struct plat_serial8250_port dm355_serial0_platform_data[] = {
|
|
{
|
|
.mapbase = DAVINCI_UART0_BASE,
|
|
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
|
|
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
|
|
UPF_IOREMAP,
|
|
.iotype = UPIO_MEM,
|
|
.regshift = 2,
|
|
},
|
|
{
|
|
.flags = 0,
|
|
}
|
|
};
|
|
static struct plat_serial8250_port dm355_serial1_platform_data[] = {
|
|
{
|
|
.mapbase = DAVINCI_UART1_BASE,
|
|
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
|
|
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
|
|
UPF_IOREMAP,
|
|
.iotype = UPIO_MEM,
|
|
.regshift = 2,
|
|
},
|
|
{
|
|
.flags = 0,
|
|
}
|
|
};
|
|
static struct plat_serial8250_port dm355_serial2_platform_data[] = {
|
|
{
|
|
.mapbase = DM355_UART2_BASE,
|
|
.irq = DAVINCI_INTC_IRQ(IRQ_DM355_UARTINT2),
|
|
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
|
|
UPF_IOREMAP,
|
|
.iotype = UPIO_MEM,
|
|
.regshift = 2,
|
|
},
|
|
{
|
|
.flags = 0,
|
|
}
|
|
};
|
|
|
|
struct platform_device dm355_serial_device[] = {
|
|
{
|
|
.name = "serial8250",
|
|
.id = PLAT8250_DEV_PLATFORM,
|
|
.dev = {
|
|
.platform_data = dm355_serial0_platform_data,
|
|
}
|
|
},
|
|
{
|
|
.name = "serial8250",
|
|
.id = PLAT8250_DEV_PLATFORM1,
|
|
.dev = {
|
|
.platform_data = dm355_serial1_platform_data,
|
|
}
|
|
},
|
|
{
|
|
.name = "serial8250",
|
|
.id = PLAT8250_DEV_PLATFORM2,
|
|
.dev = {
|
|
.platform_data = dm355_serial2_platform_data,
|
|
}
|
|
},
|
|
{
|
|
}
|
|
};
|
|
|
|
static const struct davinci_soc_info davinci_soc_info_dm355 = {
|
|
.io_desc = dm355_io_desc,
|
|
.io_desc_num = ARRAY_SIZE(dm355_io_desc),
|
|
.jtag_id_reg = 0x01c40028,
|
|
.ids = dm355_ids,
|
|
.ids_num = ARRAY_SIZE(dm355_ids),
|
|
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
|
|
.pinmux_pins = dm355_pins,
|
|
.pinmux_pins_num = ARRAY_SIZE(dm355_pins),
|
|
.sram_dma = 0x00010000,
|
|
.sram_len = SZ_32K,
|
|
};
|
|
|
|
void __init dm355_init_asp1(u32 evt_enable)
|
|
{
|
|
/* we don't use ASP1 IRQs, or we'd need to mux them ... */
|
|
if (evt_enable & ASP1_TX_EVT_EN)
|
|
davinci_cfg_reg(DM355_EVT8_ASP1_TX);
|
|
|
|
if (evt_enable & ASP1_RX_EVT_EN)
|
|
davinci_cfg_reg(DM355_EVT9_ASP1_RX);
|
|
|
|
platform_device_register(&dm355_asp1_device);
|
|
}
|
|
|
|
void __init dm355_init(void)
|
|
{
|
|
davinci_common_init(&davinci_soc_info_dm355);
|
|
davinci_map_sysmod();
|
|
}
|
|
|
|
void __init dm355_init_time(void)
|
|
{
|
|
void __iomem *pll1, *psc;
|
|
struct clk *clk;
|
|
int rv;
|
|
|
|
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ);
|
|
|
|
pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
|
|
dm355_pll1_init(NULL, pll1, NULL);
|
|
|
|
psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
|
|
dm355_psc_init(NULL, psc);
|
|
|
|
clk = clk_get(NULL, "timer0");
|
|
if (WARN_ON(IS_ERR(clk))) {
|
|
pr_err("Unable to get the timer clock\n");
|
|
return;
|
|
}
|
|
|
|
rv = davinci_timer_register(clk, &dm355_timer_cfg);
|
|
WARN(rv, "Unable to register the timer: %d\n", rv);
|
|
}
|
|
|
|
static struct resource dm355_pll2_resources[] = {
|
|
{
|
|
.start = DAVINCI_PLL2_BASE,
|
|
.end = DAVINCI_PLL2_BASE + SZ_1K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct platform_device dm355_pll2_device = {
|
|
.name = "dm355-pll2",
|
|
.id = -1,
|
|
.resource = dm355_pll2_resources,
|
|
.num_resources = ARRAY_SIZE(dm355_pll2_resources),
|
|
};
|
|
|
|
void __init dm355_register_clocks(void)
|
|
{
|
|
/* PLL1 and PSC are registered in dm355_init_time() */
|
|
platform_device_register(&dm355_pll2_device);
|
|
}
|
|
|
|
int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
|
|
struct vpbe_config *vpbe_cfg)
|
|
{
|
|
if (vpfe_cfg || vpbe_cfg)
|
|
platform_device_register(&dm355_vpss_device);
|
|
|
|
if (vpfe_cfg) {
|
|
vpfe_capture_dev.dev.platform_data = vpfe_cfg;
|
|
platform_device_register(&dm355_ccdc_dev);
|
|
platform_device_register(&vpfe_capture_dev);
|
|
}
|
|
|
|
if (vpbe_cfg) {
|
|
dm355_vpbe_dev.dev.platform_data = vpbe_cfg;
|
|
platform_device_register(&dm355_osd_dev);
|
|
platform_device_register(&dm355_venc_dev);
|
|
platform_device_register(&dm355_vpbe_dev);
|
|
platform_device_register(&dm355_vpbe_display);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct davinci_aintc_config dm355_aintc_config = {
|
|
.reg = {
|
|
.start = DAVINCI_ARM_INTC_BASE,
|
|
.end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
.num_irqs = 64,
|
|
.prios = dm355_default_priorities,
|
|
};
|
|
|
|
void __init dm355_init_irq(void)
|
|
{
|
|
davinci_aintc_init(&dm355_aintc_config);
|
|
}
|
|
|
|
static int __init dm355_init_devices(void)
|
|
{
|
|
struct platform_device *edma_pdev;
|
|
int ret = 0;
|
|
|
|
if (!cpu_is_davinci_dm355())
|
|
return 0;
|
|
|
|
davinci_cfg_reg(DM355_INT_EDMA_CC);
|
|
edma_pdev = platform_device_register_full(&dm355_edma_device);
|
|
if (IS_ERR(edma_pdev)) {
|
|
pr_warn("%s: Failed to register eDMA\n", __func__);
|
|
return PTR_ERR(edma_pdev);
|
|
}
|
|
|
|
ret = davinci_init_wdt();
|
|
if (ret)
|
|
pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
|
|
|
|
return ret;
|
|
}
|
|
postcore_initcall(dm355_init_devices);
|