205 lines
9.7 KiB
C
205 lines
9.7 KiB
C
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/* SPDX-License-Identifier: LGPL-2.1 OR MIT */
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/*
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* RISCV (32 and 64) specific definitions for NOLIBC
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* Copyright (C) 2017-2022 Willy Tarreau <w@1wt.eu>
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*/
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#ifndef _NOLIBC_ARCH_RISCV_H
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#define _NOLIBC_ARCH_RISCV_H
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/* O_* macros for fcntl/open are architecture-specific */
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#define O_RDONLY 0
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#define O_WRONLY 1
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#define O_RDWR 2
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#define O_CREAT 0x40
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#define O_EXCL 0x80
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#define O_NOCTTY 0x100
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#define O_TRUNC 0x200
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#define O_APPEND 0x400
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#define O_NONBLOCK 0x800
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#define O_DIRECTORY 0x10000
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struct sys_stat_struct {
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unsigned long st_dev; /* Device. */
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unsigned long st_ino; /* File serial number. */
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unsigned int st_mode; /* File mode. */
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unsigned int st_nlink; /* Link count. */
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unsigned int st_uid; /* User ID of the file's owner. */
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unsigned int st_gid; /* Group ID of the file's group. */
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unsigned long st_rdev; /* Device number, if device. */
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unsigned long __pad1;
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long st_size; /* Size of file, in bytes. */
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int st_blksize; /* Optimal block size for I/O. */
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int __pad2;
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long st_blocks; /* Number 512-byte blocks allocated. */
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long st_atime; /* Time of last access. */
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unsigned long st_atime_nsec;
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long st_mtime; /* Time of last modification. */
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unsigned long st_mtime_nsec;
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long st_ctime; /* Time of last status change. */
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unsigned long st_ctime_nsec;
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unsigned int __unused4;
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unsigned int __unused5;
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};
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#if __riscv_xlen == 64
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#define PTRLOG "3"
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#define SZREG "8"
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#elif __riscv_xlen == 32
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#define PTRLOG "2"
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#define SZREG "4"
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#endif
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/* Syscalls for RISCV :
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* - stack is 16-byte aligned
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* - syscall number is passed in a7
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* - arguments are in a0, a1, a2, a3, a4, a5
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* - the system call is performed by calling ecall
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* - syscall return comes in a0
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* - the arguments are cast to long and assigned into the target
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* registers which are then simply passed as registers to the asm code,
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* so that we don't have to experience issues with register constraints.
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*
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* On riscv, select() is not implemented so we have to use pselect6().
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*/
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#define __ARCH_WANT_SYS_PSELECT6
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#define my_syscall0(num) \
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({ \
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register long _num asm("a7") = (num); \
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register long _arg1 asm("a0"); \
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\
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asm volatile ( \
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"ecall\n\t" \
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: "=r"(_arg1) \
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: "r"(_num) \
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: "memory", "cc" \
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); \
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_arg1; \
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})
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#define my_syscall1(num, arg1) \
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({ \
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register long _num asm("a7") = (num); \
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register long _arg1 asm("a0") = (long)(arg1); \
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\
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asm volatile ( \
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"ecall\n" \
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: "+r"(_arg1) \
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: "r"(_num) \
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: "memory", "cc" \
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); \
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_arg1; \
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})
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#define my_syscall2(num, arg1, arg2) \
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({ \
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register long _num asm("a7") = (num); \
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register long _arg1 asm("a0") = (long)(arg1); \
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register long _arg2 asm("a1") = (long)(arg2); \
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\
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asm volatile ( \
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"ecall\n" \
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: "+r"(_arg1) \
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: "r"(_arg2), \
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"r"(_num) \
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: "memory", "cc" \
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); \
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_arg1; \
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})
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#define my_syscall3(num, arg1, arg2, arg3) \
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({ \
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register long _num asm("a7") = (num); \
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register long _arg1 asm("a0") = (long)(arg1); \
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register long _arg2 asm("a1") = (long)(arg2); \
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register long _arg3 asm("a2") = (long)(arg3); \
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\
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asm volatile ( \
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"ecall\n\t" \
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: "+r"(_arg1) \
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: "r"(_arg2), "r"(_arg3), \
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"r"(_num) \
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: "memory", "cc" \
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); \
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_arg1; \
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})
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#define my_syscall4(num, arg1, arg2, arg3, arg4) \
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({ \
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register long _num asm("a7") = (num); \
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register long _arg1 asm("a0") = (long)(arg1); \
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register long _arg2 asm("a1") = (long)(arg2); \
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register long _arg3 asm("a2") = (long)(arg3); \
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register long _arg4 asm("a3") = (long)(arg4); \
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\
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asm volatile ( \
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"ecall\n" \
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: "+r"(_arg1) \
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: "r"(_arg2), "r"(_arg3), "r"(_arg4), \
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"r"(_num) \
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: "memory", "cc" \
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); \
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_arg1; \
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})
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#define my_syscall5(num, arg1, arg2, arg3, arg4, arg5) \
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({ \
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register long _num asm("a7") = (num); \
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register long _arg1 asm("a0") = (long)(arg1); \
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register long _arg2 asm("a1") = (long)(arg2); \
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register long _arg3 asm("a2") = (long)(arg3); \
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register long _arg4 asm("a3") = (long)(arg4); \
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register long _arg5 asm("a4") = (long)(arg5); \
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\
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asm volatile ( \
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"ecall\n" \
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: "+r"(_arg1) \
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: "r"(_arg2), "r"(_arg3), "r"(_arg4), "r"(_arg5), \
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"r"(_num) \
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: "memory", "cc" \
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); \
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_arg1; \
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})
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#define my_syscall6(num, arg1, arg2, arg3, arg4, arg5, arg6) \
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({ \
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register long _num asm("a7") = (num); \
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register long _arg1 asm("a0") = (long)(arg1); \
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register long _arg2 asm("a1") = (long)(arg2); \
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register long _arg3 asm("a2") = (long)(arg3); \
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register long _arg4 asm("a3") = (long)(arg4); \
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register long _arg5 asm("a4") = (long)(arg5); \
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register long _arg6 asm("a5") = (long)(arg6); \
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\
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asm volatile ( \
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"ecall\n" \
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: "+r"(_arg1) \
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: "r"(_arg2), "r"(_arg3), "r"(_arg4), "r"(_arg5), "r"(_arg6), \
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"r"(_num) \
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: "memory", "cc" \
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); \
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_arg1; \
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})
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/* startup code */
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asm(".section .text\n"
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".weak _start\n"
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"_start:\n"
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".option push\n"
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".option norelax\n"
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"lla gp, __global_pointer$\n"
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".option pop\n"
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"ld a0, 0(sp)\n" // argc (a0) was in the stack
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"add a1, sp, "SZREG"\n" // argv (a1) = sp
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"slli a2, a0, "PTRLOG"\n" // envp (a2) = SZREG*argc ...
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"add a2, a2, "SZREG"\n" // + SZREG (skip null)
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"add a2,a2,a1\n" // + argv
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"andi sp,a1,-16\n" // sp must be 16-byte aligned
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"call main\n" // main() returns the status code, we'll exit with it.
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"li a7, 93\n" // NR_exit == 93
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"ecall\n"
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"");
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#endif // _NOLIBC_ARCH_RISCV_H
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