75 lines
2.2 KiB
C
75 lines
2.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef DT_BINDINGS_MEMORY_TEGRA20_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA20_MC_H
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#define TEGRA20_MC_RESET_AVPC 0
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#define TEGRA20_MC_RESET_DC 1
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#define TEGRA20_MC_RESET_DCB 2
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#define TEGRA20_MC_RESET_EPP 3
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#define TEGRA20_MC_RESET_2D 4
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#define TEGRA20_MC_RESET_HC 5
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#define TEGRA20_MC_RESET_ISP 6
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#define TEGRA20_MC_RESET_MPCORE 7
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#define TEGRA20_MC_RESET_MPEA 8
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#define TEGRA20_MC_RESET_MPEB 9
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#define TEGRA20_MC_RESET_MPEC 10
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#define TEGRA20_MC_RESET_3D 11
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#define TEGRA20_MC_RESET_PPCS 12
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#define TEGRA20_MC_RESET_VDE 13
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#define TEGRA20_MC_RESET_VI 14
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#define TEGRA20_MC_DISPLAY0A 0
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#define TEGRA20_MC_DISPLAY0AB 1
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#define TEGRA20_MC_DISPLAY0B 2
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#define TEGRA20_MC_DISPLAY0BB 3
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#define TEGRA20_MC_DISPLAY0C 4
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#define TEGRA20_MC_DISPLAY0CB 5
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#define TEGRA20_MC_DISPLAY1B 6
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#define TEGRA20_MC_DISPLAY1BB 7
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#define TEGRA20_MC_EPPUP 8
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#define TEGRA20_MC_G2PR 9
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#define TEGRA20_MC_G2SR 10
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#define TEGRA20_MC_MPEUNIFBR 11
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#define TEGRA20_MC_VIRUV 12
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#define TEGRA20_MC_AVPCARM7R 13
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#define TEGRA20_MC_DISPLAYHC 14
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#define TEGRA20_MC_DISPLAYHCB 15
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#define TEGRA20_MC_FDCDRD 16
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#define TEGRA20_MC_G2DR 17
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#define TEGRA20_MC_HOST1XDMAR 18
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#define TEGRA20_MC_HOST1XR 19
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#define TEGRA20_MC_IDXSRD 20
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#define TEGRA20_MC_MPCORER 21
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#define TEGRA20_MC_MPE_IPRED 22
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#define TEGRA20_MC_MPEAMEMRD 23
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#define TEGRA20_MC_MPECSRD 24
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#define TEGRA20_MC_PPCSAHBDMAR 25
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#define TEGRA20_MC_PPCSAHBSLVR 26
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#define TEGRA20_MC_TEXSRD 27
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#define TEGRA20_MC_VDEBSEVR 28
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#define TEGRA20_MC_VDEMBER 29
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#define TEGRA20_MC_VDEMCER 30
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#define TEGRA20_MC_VDETPER 31
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#define TEGRA20_MC_EPPU 32
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#define TEGRA20_MC_EPPV 33
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#define TEGRA20_MC_EPPY 34
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#define TEGRA20_MC_MPEUNIFBW 35
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#define TEGRA20_MC_VIWSB 36
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#define TEGRA20_MC_VIWU 37
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#define TEGRA20_MC_VIWV 38
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#define TEGRA20_MC_VIWY 39
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#define TEGRA20_MC_G2DW 40
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#define TEGRA20_MC_AVPCARM7W 41
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#define TEGRA20_MC_FDCDWR 42
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#define TEGRA20_MC_HOST1XW 43
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#define TEGRA20_MC_ISPW 44
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#define TEGRA20_MC_MPCOREW 45
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#define TEGRA20_MC_MPECSWR 46
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#define TEGRA20_MC_PPCSAHBDMAW 47
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#define TEGRA20_MC_PPCSAHBSLVW 48
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#define TEGRA20_MC_VDEBSEVW 49
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#define TEGRA20_MC_VDEMBEW 50
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#define TEGRA20_MC_VDETPMW 51
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#endif
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