163 lines
4.6 KiB
C
163 lines
4.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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*
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* (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
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*
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* Parts of this file were based on sources as follows:
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*
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* Copyright (c) 2006-2008 Intel Corporation
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* Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
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* Copyright (C) 2011 Texas Instruments
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*/
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#ifndef _PL111_DRM_H_
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#define _PL111_DRM_H_
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#include <linux/clk-provider.h>
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#include <linux/interrupt.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_connector.h>
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#include <drm/drm_encoder.h>
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#include <drm/drm_gem.h>
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#include <drm/drm_panel.h>
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#include <drm/drm_simple_kms_helper.h>
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/*
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* CLCD Controller Internal Register addresses
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*/
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#define CLCD_TIM0 0x00000000
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#define CLCD_TIM1 0x00000004
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#define CLCD_TIM2 0x00000008
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#define CLCD_TIM3 0x0000000c
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#define CLCD_UBAS 0x00000010
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#define CLCD_LBAS 0x00000014
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#define CLCD_PL110_IENB 0x00000018
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#define CLCD_PL110_CNTL 0x0000001c
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#define CLCD_PL110_STAT 0x00000020
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#define CLCD_PL110_INTR 0x00000024
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#define CLCD_PL110_UCUR 0x00000028
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#define CLCD_PL110_LCUR 0x0000002C
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#define CLCD_PL111_CNTL 0x00000018
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#define CLCD_PL111_IENB 0x0000001c
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#define CLCD_PL111_RIS 0x00000020
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#define CLCD_PL111_MIS 0x00000024
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#define CLCD_PL111_ICR 0x00000028
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#define CLCD_PL111_UCUR 0x0000002c
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#define CLCD_PL111_LCUR 0x00000030
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#define CLCD_PALL 0x00000200
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#define CLCD_PALETTE 0x00000200
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#define TIM2_PCD_LO_MASK GENMASK(4, 0)
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#define TIM2_PCD_LO_BITS 5
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#define TIM2_CLKSEL (1 << 5)
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#define TIM2_ACB_MASK GENMASK(10, 6)
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#define TIM2_IVS (1 << 11)
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#define TIM2_IHS (1 << 12)
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#define TIM2_IPC (1 << 13)
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#define TIM2_IOE (1 << 14)
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#define TIM2_BCD (1 << 26)
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#define TIM2_PCD_HI_MASK GENMASK(31, 27)
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#define TIM2_PCD_HI_BITS 5
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#define TIM2_PCD_HI_SHIFT 27
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#define CNTL_LCDEN (1 << 0)
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#define CNTL_LCDBPP1 (0 << 1)
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#define CNTL_LCDBPP2 (1 << 1)
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#define CNTL_LCDBPP4 (2 << 1)
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#define CNTL_LCDBPP8 (3 << 1)
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#define CNTL_LCDBPP16 (4 << 1)
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#define CNTL_LCDBPP16_565 (6 << 1)
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#define CNTL_LCDBPP16_444 (7 << 1)
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#define CNTL_LCDBPP24 (5 << 1)
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#define CNTL_LCDBW (1 << 4)
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#define CNTL_LCDTFT (1 << 5)
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#define CNTL_LCDMONO8 (1 << 6)
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#define CNTL_LCDDUAL (1 << 7)
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#define CNTL_BGR (1 << 8)
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#define CNTL_BEBO (1 << 9)
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#define CNTL_BEPO (1 << 10)
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#define CNTL_LCDPWR (1 << 11)
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#define CNTL_LCDVCOMP(x) ((x) << 12)
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#define CNTL_LDMAFIFOTIME (1 << 15)
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#define CNTL_WATERMARK (1 << 16)
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/* ST Microelectronics variant bits */
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#define CNTL_ST_1XBPP_444 0x0
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#define CNTL_ST_1XBPP_5551 (1 << 17)
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#define CNTL_ST_1XBPP_565 (1 << 18)
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#define CNTL_ST_CDWID_12 0x0
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#define CNTL_ST_CDWID_16 (1 << 19)
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#define CNTL_ST_CDWID_18 (1 << 20)
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#define CNTL_ST_CDWID_24 ((1 << 19) | (1 << 20))
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#define CNTL_ST_CEAEN (1 << 21)
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#define CNTL_ST_LCDBPP24_PACKED (6 << 1)
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#define CLCD_IRQ_NEXTBASE_UPDATE BIT(2)
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struct drm_minor;
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/**
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* struct pl111_variant_data - encodes IP differences
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* @name: the name of this variant
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* @is_pl110: this is the early PL110 variant
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* @is_lcdc: this is the ST Microelectronics Nomadik LCDC variant
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* @external_bgr: this is the Versatile Pl110 variant with external
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* BGR/RGB routing
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* @broken_clockdivider: the clock divider is broken and we need to
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* use the supplied clock directly
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* @broken_vblank: the vblank IRQ is broken on this variant
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* @st_bitmux_control: this variant is using the ST Micro bitmux
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* extensions to the control register
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* @formats: array of supported pixel formats on this variant
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* @nformats: the length of the array of supported pixel formats
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* @fb_bpp: desired bits per pixel on the default framebuffer
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*/
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struct pl111_variant_data {
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const char *name;
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bool is_pl110;
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bool is_lcdc;
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bool external_bgr;
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bool broken_clockdivider;
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bool broken_vblank;
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bool st_bitmux_control;
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const u32 *formats;
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unsigned int nformats;
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unsigned int fb_bpp;
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};
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struct pl111_drm_dev_private {
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struct drm_device *drm;
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struct drm_connector *connector;
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struct drm_panel *panel;
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struct drm_bridge *bridge;
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struct drm_simple_display_pipe pipe;
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void *regs;
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u32 memory_bw;
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u32 ienb;
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u32 ctrl;
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/* The pixel clock (a reference to our clock divider off of CLCDCLK). */
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struct clk *clk;
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/* pl111's internal clock divider. */
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struct clk_hw clk_div;
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/* Lock to sync access to CLCD_TIM2 between the common clock
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* subsystem and pl111_display_enable().
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*/
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spinlock_t tim2_lock;
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const struct pl111_variant_data *variant;
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void (*variant_display_enable) (struct drm_device *drm, u32 format);
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void (*variant_display_disable) (struct drm_device *drm);
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bool use_device_memory;
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};
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int pl111_display_init(struct drm_device *dev);
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irqreturn_t pl111_irq(int irq, void *data);
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void pl111_debugfs_init(struct drm_minor *minor);
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#endif /* _PL111_DRM_H_ */
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