351 lines
11 KiB
C
351 lines
11 KiB
C
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/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include <core/memory.h>
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#include <subdev/acr.h>
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#include <subdev/timer.h>
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#include <nvfw/flcn.h>
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#include <nvfw/sec2.h>
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int
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gp102_sec2_nofw(struct nvkm_sec2 *sec2, int ver,
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const struct nvkm_sec2_fwif *fwif)
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{
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nvkm_warn(&sec2->engine.subdev, "firmware unavailable\n");
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return 0;
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}
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static int
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gp102_sec2_acr_bootstrap_falcon_callback(void *priv, struct nvfw_falcon_msg *hdr)
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{
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struct nv_sec2_acr_bootstrap_falcon_msg *msg =
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container_of(hdr, typeof(*msg), msg.hdr);
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struct nvkm_subdev *subdev = priv;
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const char *name = nvkm_acr_lsf_id(msg->falcon_id);
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if (msg->error_code) {
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nvkm_error(subdev, "ACR_BOOTSTRAP_FALCON failed for "
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"falcon %d [%s]: %08x\n",
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msg->falcon_id, name, msg->error_code);
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return -EINVAL;
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}
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nvkm_debug(subdev, "%s booted\n", name);
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return 0;
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}
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static int
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gp102_sec2_acr_bootstrap_falcon(struct nvkm_falcon *falcon,
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enum nvkm_acr_lsf_id id)
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{
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struct nvkm_sec2 *sec2 = container_of(falcon, typeof(*sec2), falcon);
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struct nv_sec2_acr_bootstrap_falcon_cmd cmd = {
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.cmd.hdr.unit_id = sec2->func->unit_acr,
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.cmd.hdr.size = sizeof(cmd),
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.cmd.cmd_type = NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON,
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.flags = NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES,
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.falcon_id = id,
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};
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return nvkm_falcon_cmdq_send(sec2->cmdq, &cmd.cmd.hdr,
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gp102_sec2_acr_bootstrap_falcon_callback,
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&sec2->engine.subdev,
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msecs_to_jiffies(1000));
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}
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static int
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gp102_sec2_acr_boot(struct nvkm_falcon *falcon)
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{
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struct nv_sec2_args args = {};
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nvkm_falcon_load_dmem(falcon, &args,
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falcon->func->emem_addr, sizeof(args), 0);
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nvkm_falcon_start(falcon);
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return 0;
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}
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static void
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gp102_sec2_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
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{
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struct loader_config_v1 hdr;
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nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
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hdr.code_dma_base = hdr.code_dma_base + adjust;
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hdr.data_dma_base = hdr.data_dma_base + adjust;
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hdr.overlay_dma_base = hdr.overlay_dma_base + adjust;
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nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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loader_config_v1_dump(&acr->subdev, &hdr);
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}
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static void
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gp102_sec2_acr_bld_write(struct nvkm_acr *acr, u32 bld,
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struct nvkm_acr_lsfw *lsfw)
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{
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const struct loader_config_v1 hdr = {
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.dma_idx = FALCON_SEC2_DMAIDX_UCODE,
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.code_dma_base = lsfw->offset.img + lsfw->app_start_offset,
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.code_size_total = lsfw->app_size,
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.code_size_to_load = lsfw->app_resident_code_size,
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.code_entry_point = lsfw->app_imem_entry,
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.data_dma_base = lsfw->offset.img + lsfw->app_start_offset +
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lsfw->app_resident_data_offset,
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.data_size = lsfw->app_resident_data_size,
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.overlay_dma_base = lsfw->offset.img + lsfw->app_start_offset,
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.argc = 1,
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.argv = lsfw->falcon->func->emem_addr,
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};
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nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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}
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static const struct nvkm_acr_lsf_func
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gp102_sec2_acr_0 = {
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.bld_size = sizeof(struct loader_config_v1),
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.bld_write = gp102_sec2_acr_bld_write,
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.bld_patch = gp102_sec2_acr_bld_patch,
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.boot = gp102_sec2_acr_boot,
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.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) |
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BIT_ULL(NVKM_ACR_LSF_GPCCS) |
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BIT_ULL(NVKM_ACR_LSF_SEC2),
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.bootstrap_falcon = gp102_sec2_acr_bootstrap_falcon,
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};
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int
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gp102_sec2_initmsg(struct nvkm_sec2 *sec2)
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{
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struct nv_sec2_init_msg msg;
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int ret, i;
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ret = nvkm_falcon_msgq_recv_initmsg(sec2->msgq, &msg, sizeof(msg));
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if (ret)
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return ret;
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if (msg.hdr.unit_id != NV_SEC2_UNIT_INIT ||
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msg.msg_type != NV_SEC2_INIT_MSG_INIT)
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(msg.queue_info); i++) {
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if (msg.queue_info[i].id == NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ) {
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nvkm_falcon_msgq_init(sec2->msgq,
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msg.queue_info[i].index,
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msg.queue_info[i].offset,
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msg.queue_info[i].size);
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} else {
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nvkm_falcon_cmdq_init(sec2->cmdq,
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msg.queue_info[i].index,
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msg.queue_info[i].offset,
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msg.queue_info[i].size);
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}
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}
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return 0;
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}
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void
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gp102_sec2_intr(struct nvkm_sec2 *sec2)
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{
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struct nvkm_subdev *subdev = &sec2->engine.subdev;
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struct nvkm_falcon *falcon = &sec2->falcon;
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u32 disp = nvkm_falcon_rd32(falcon, 0x01c);
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u32 intr = nvkm_falcon_rd32(falcon, 0x008) & disp & ~(disp >> 16);
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if (intr & 0x00000040) {
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schedule_work(&sec2->work);
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nvkm_falcon_wr32(falcon, 0x004, 0x00000040);
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intr &= ~0x00000040;
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}
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if (intr) {
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nvkm_error(subdev, "unhandled intr %08x\n", intr);
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nvkm_falcon_wr32(falcon, 0x004, intr);
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}
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}
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int
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gp102_sec2_flcn_enable(struct nvkm_falcon *falcon)
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{
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nvkm_falcon_mask(falcon, 0x3c0, 0x00000001, 0x00000001);
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udelay(10);
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nvkm_falcon_mask(falcon, 0x3c0, 0x00000001, 0x00000000);
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return nvkm_falcon_v1_enable(falcon);
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}
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void
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gp102_sec2_flcn_bind_context(struct nvkm_falcon *falcon,
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struct nvkm_memory *ctx)
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{
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struct nvkm_device *device = falcon->owner->device;
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nvkm_falcon_v1_bind_context(falcon, ctx);
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if (!ctx)
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return;
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/* Not sure if this is a WAR for a HW issue, or some additional
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* programming sequence that's needed to properly complete the
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* context switch we trigger above.
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*
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* Fixes unreliability of booting the SEC2 RTOS on Quadro P620,
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* particularly when resuming from suspend.
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*
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* Also removes the need for an odd workaround where we needed
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* to program SEC2's FALCON_CPUCTL_ALIAS_STARTCPU twice before
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* the SEC2 RTOS would begin executing.
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*/
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nvkm_msec(device, 10,
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u32 irqstat = nvkm_falcon_rd32(falcon, 0x008);
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u32 flcn0dc = nvkm_falcon_rd32(falcon, 0x0dc);
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if ((irqstat & 0x00000008) &&
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(flcn0dc & 0x00007000) == 0x00005000)
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break;
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);
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nvkm_falcon_mask(falcon, 0x004, 0x00000008, 0x00000008);
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nvkm_falcon_mask(falcon, 0x058, 0x00000002, 0x00000002);
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nvkm_msec(device, 10,
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u32 flcn0dc = nvkm_falcon_rd32(falcon, 0x0dc);
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if ((flcn0dc & 0x00007000) == 0x00000000)
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break;
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);
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}
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static const struct nvkm_falcon_func
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gp102_sec2_flcn = {
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.debug = 0x408,
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.fbif = 0x600,
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.load_imem = nvkm_falcon_v1_load_imem,
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.load_dmem = nvkm_falcon_v1_load_dmem,
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.read_dmem = nvkm_falcon_v1_read_dmem,
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.emem_addr = 0x01000000,
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.bind_context = gp102_sec2_flcn_bind_context,
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.wait_for_halt = nvkm_falcon_v1_wait_for_halt,
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.clear_interrupt = nvkm_falcon_v1_clear_interrupt,
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.set_start_addr = nvkm_falcon_v1_set_start_addr,
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.start = nvkm_falcon_v1_start,
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.enable = gp102_sec2_flcn_enable,
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.disable = nvkm_falcon_v1_disable,
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.cmdq = { 0xa00, 0xa04, 8 },
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.msgq = { 0xa30, 0xa34, 8 },
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};
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const struct nvkm_sec2_func
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gp102_sec2 = {
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.flcn = &gp102_sec2_flcn,
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.unit_acr = NV_SEC2_UNIT_ACR,
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.intr = gp102_sec2_intr,
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.initmsg = gp102_sec2_initmsg,
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};
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MODULE_FIRMWARE("nvidia/gp102/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/gp102/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/gp102/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/gp104/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/gp104/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/gp104/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/gp106/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/gp106/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/gp106/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/gp107/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/gp107/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/gp107/sec2/sig.bin");
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static void
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gp102_sec2_acr_bld_patch_1(struct nvkm_acr *acr, u32 bld, s64 adjust)
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{
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struct flcn_bl_dmem_desc_v2 hdr;
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nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
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hdr.code_dma_base = hdr.code_dma_base + adjust;
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hdr.data_dma_base = hdr.data_dma_base + adjust;
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nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hdr);
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}
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static void
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gp102_sec2_acr_bld_write_1(struct nvkm_acr *acr, u32 bld,
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struct nvkm_acr_lsfw *lsfw)
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{
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const struct flcn_bl_dmem_desc_v2 hdr = {
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.ctx_dma = FALCON_SEC2_DMAIDX_UCODE,
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.code_dma_base = lsfw->offset.img + lsfw->app_start_offset,
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.non_sec_code_off = lsfw->app_resident_code_offset,
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.non_sec_code_size = lsfw->app_resident_code_size,
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.code_entry_point = lsfw->app_imem_entry,
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.data_dma_base = lsfw->offset.img + lsfw->app_start_offset +
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lsfw->app_resident_data_offset,
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.data_size = lsfw->app_resident_data_size,
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.argc = 1,
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.argv = lsfw->falcon->func->emem_addr,
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};
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nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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}
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const struct nvkm_acr_lsf_func
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gp102_sec2_acr_1 = {
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.bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
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.bld_write = gp102_sec2_acr_bld_write_1,
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.bld_patch = gp102_sec2_acr_bld_patch_1,
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.boot = gp102_sec2_acr_boot,
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.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) |
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BIT_ULL(NVKM_ACR_LSF_GPCCS) |
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BIT_ULL(NVKM_ACR_LSF_SEC2),
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.bootstrap_falcon = gp102_sec2_acr_bootstrap_falcon,
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};
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int
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gp102_sec2_load(struct nvkm_sec2 *sec2, int ver,
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const struct nvkm_sec2_fwif *fwif)
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{
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return nvkm_acr_lsfw_load_sig_image_desc_v1(&sec2->engine.subdev,
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&sec2->falcon,
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NVKM_ACR_LSF_SEC2, "sec2/",
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ver, fwif->acr);
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}
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MODULE_FIRMWARE("nvidia/gp102/sec2/desc-1.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gp102/sec2/image-1.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gp102/sec2/sig-1.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gp104/sec2/desc-1.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gp104/sec2/image-1.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gp104/sec2/sig-1.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gp106/sec2/desc-1.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gp106/sec2/image-1.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gp106/sec2/sig-1.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gp107/sec2/desc-1.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gp107/sec2/image-1.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gp107/sec2/sig-1.bin");
|
||
|
|
|
||
|
|
static const struct nvkm_sec2_fwif
|
||
|
|
gp102_sec2_fwif[] = {
|
||
|
|
{ 1, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_1 },
|
||
|
|
{ 0, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_0 },
|
||
|
|
{ -1, gp102_sec2_nofw, &gp102_sec2 },
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
|
||
|
|
int
|
||
|
|
gp102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
|
||
|
|
struct nvkm_sec2 **psec2)
|
||
|
|
{
|
||
|
|
return nvkm_sec2_new_(gp102_sec2_fwif, device, type, inst, 0, psec2);
|
||
|
|
}
|