364 lines
9.0 KiB
C
364 lines
9.0 KiB
C
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/*
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* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "gf100.h"
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#include "ctxgf100.h"
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#include <core/firmware.h>
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#include <subdev/timer.h>
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#include <nvif/class.h>
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struct gk20a_fw_av
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{
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u32 addr;
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u32 data;
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};
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static int
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gk20a_gr_av_to_init(struct gf100_gr *gr, const char *path, const char *name,
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int ver, struct gf100_gr_pack **ppack)
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{
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struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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struct nvkm_blob blob;
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struct gf100_gr_init *init;
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struct gf100_gr_pack *pack;
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int nent;
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int ret;
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int i;
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ret = nvkm_firmware_load_blob(subdev, path, name, ver, &blob);
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if (ret)
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return ret;
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nent = (blob.size / sizeof(struct gk20a_fw_av));
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pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1)));
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if (!pack) {
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ret = -ENOMEM;
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goto end;
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}
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init = (void *)(pack + 2);
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pack[0].init = init;
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for (i = 0; i < nent; i++) {
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struct gf100_gr_init *ent = &init[i];
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struct gk20a_fw_av *av = &((struct gk20a_fw_av *)blob.data)[i];
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ent->addr = av->addr;
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ent->data = av->data;
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ent->count = 1;
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ent->pitch = 1;
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}
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*ppack = pack;
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end:
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nvkm_blob_dtor(&blob);
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return ret;
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}
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struct gk20a_fw_aiv
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{
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u32 addr;
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u32 index;
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u32 data;
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};
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static int
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gk20a_gr_aiv_to_init(struct gf100_gr *gr, const char *path, const char *name,
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int ver, struct gf100_gr_pack **ppack)
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{
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struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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struct nvkm_blob blob;
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struct gf100_gr_init *init;
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struct gf100_gr_pack *pack;
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int nent;
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int ret;
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int i;
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ret = nvkm_firmware_load_blob(subdev, path, name, ver, &blob);
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if (ret)
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return ret;
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nent = (blob.size / sizeof(struct gk20a_fw_aiv));
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pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1)));
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if (!pack) {
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ret = -ENOMEM;
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goto end;
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}
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init = (void *)(pack + 2);
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pack[0].init = init;
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for (i = 0; i < nent; i++) {
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struct gf100_gr_init *ent = &init[i];
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struct gk20a_fw_aiv *av = &((struct gk20a_fw_aiv *)blob.data)[i];
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ent->addr = av->addr;
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ent->data = av->data;
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ent->count = 1;
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ent->pitch = 1;
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}
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*ppack = pack;
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end:
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nvkm_blob_dtor(&blob);
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return ret;
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}
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static int
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gk20a_gr_av_to_method(struct gf100_gr *gr, const char *path, const char *name,
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int ver, struct gf100_gr_pack **ppack)
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{
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struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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struct nvkm_blob blob;
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struct gf100_gr_init *init;
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struct gf100_gr_pack *pack;
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/* We don't suppose we will initialize more than 16 classes here... */
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static const unsigned int max_classes = 16;
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u32 classidx = 0, prevclass = 0;
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int nent;
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int ret;
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int i;
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ret = nvkm_firmware_load_blob(subdev, path, name, ver, &blob);
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if (ret)
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return ret;
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nent = (blob.size / sizeof(struct gk20a_fw_av));
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pack = vzalloc((sizeof(*pack) * (max_classes + 1)) +
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(sizeof(*init) * (nent + max_classes + 1)));
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if (!pack) {
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ret = -ENOMEM;
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goto end;
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}
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init = (void *)(pack + max_classes + 1);
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for (i = 0; i < nent; i++, init++) {
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struct gk20a_fw_av *av = &((struct gk20a_fw_av *)blob.data)[i];
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u32 class = av->addr & 0xffff;
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u32 addr = (av->addr & 0xffff0000) >> 14;
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if (prevclass != class) {
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if (prevclass) /* Add terminator to the method list. */
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init++;
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pack[classidx].init = init;
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pack[classidx].type = class;
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prevclass = class;
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if (++classidx >= max_classes) {
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vfree(pack);
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ret = -ENOSPC;
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goto end;
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}
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}
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init->addr = addr;
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init->data = av->data;
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init->count = 1;
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init->pitch = 1;
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}
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*ppack = pack;
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end:
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nvkm_blob_dtor(&blob);
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return ret;
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}
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static int
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gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr)
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{
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struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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if (nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x40910c) & 0x00000006))
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break;
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) < 0) {
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nvkm_error(subdev, "FECS mem scrubbing timeout\n");
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return -ETIMEDOUT;
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}
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if (nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x41a10c) & 0x00000006))
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break;
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) < 0) {
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nvkm_error(subdev, "GPCCS mem scrubbing timeout\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static void
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gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_wr32(device, 0x419e44, 0x1ffffe);
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nvkm_wr32(device, 0x419e4c, 0x7f);
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}
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int
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gk20a_gr_init(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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int ret;
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/* Clear SCC RAM */
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nvkm_wr32(device, 0x40802c, 0x1);
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gf100_gr_mmio(gr, gr->sw_nonctx);
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ret = gk20a_gr_wait_mem_scrubbing(gr);
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if (ret)
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return ret;
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ret = gf100_gr_wait_idle(gr);
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if (ret)
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return ret;
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/* MMU debug buffer */
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if (gr->func->init_gpc_mmu)
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gr->func->init_gpc_mmu(gr);
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/* Set the PE as stream master */
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nvkm_mask(device, 0x503018, 0x1, 0x1);
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/* Zcull init */
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gr->func->init_zcull(gr);
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gr->func->init_rop_active_fbps(gr);
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/* Enable FIFO access */
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nvkm_wr32(device, 0x400500, 0x00010001);
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/* Enable interrupts */
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nvkm_wr32(device, 0x400100, 0xffffffff);
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nvkm_wr32(device, 0x40013c, 0xffffffff);
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/* Enable FECS error interrupts */
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nvkm_wr32(device, 0x409c24, 0x000f0000);
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/* Enable hardware warning exceptions */
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nvkm_wr32(device, 0x404000, 0xc0000000);
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nvkm_wr32(device, 0x404600, 0xc0000000);
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if (gr->func->set_hww_esr_report_mask)
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gr->func->set_hww_esr_report_mask(gr);
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/* Enable TPC exceptions per GPC */
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nvkm_wr32(device, 0x419d0c, 0x2);
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nvkm_wr32(device, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16);
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/* Reset and enable all exceptions */
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nvkm_wr32(device, 0x400108, 0xffffffff);
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nvkm_wr32(device, 0x400138, 0xffffffff);
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nvkm_wr32(device, 0x400118, 0xffffffff);
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nvkm_wr32(device, 0x400130, 0xffffffff);
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nvkm_wr32(device, 0x40011c, 0xffffffff);
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nvkm_wr32(device, 0x400134, 0xffffffff);
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gf100_gr_zbc_init(gr);
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return gf100_gr_init_ctxctl(gr);
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}
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static const struct gf100_gr_func
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gk20a_gr = {
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.oneinit_tiles = gf100_gr_oneinit_tiles,
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.oneinit_sm_id = gf100_gr_oneinit_sm_id,
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.init = gk20a_gr_init,
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.init_zcull = gf117_gr_init_zcull,
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.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
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.trap_mp = gf100_gr_trap_mp,
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.set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask,
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.rops = gf100_gr_rops,
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.ppc_nr = 1,
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.grctx = &gk20a_grctx,
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.zbc = &gf100_gr_zbc,
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.sclass = {
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{ -1, -1, FERMI_TWOD_A },
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{ -1, -1, KEPLER_INLINE_TO_MEMORY_A },
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{ -1, -1, KEPLER_C, &gf100_fermi },
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{ -1, -1, KEPLER_COMPUTE_A },
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{}
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}
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};
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int
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gk20a_gr_load_sw(struct gf100_gr *gr, const char *path, int ver)
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{
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if (gk20a_gr_av_to_init(gr, path, "sw_nonctx", ver, &gr->sw_nonctx) ||
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gk20a_gr_aiv_to_init(gr, path, "sw_ctx", ver, &gr->sw_ctx) ||
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gk20a_gr_av_to_init(gr, path, "sw_bundle_init", ver, &gr->bundle) ||
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gk20a_gr_av_to_method(gr, path, "sw_method_init", ver, &gr->method))
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return -ENOENT;
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return 0;
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}
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) || IS_ENABLED(CONFIG_ARCH_TEGRA_132_SOC)
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MODULE_FIRMWARE("nvidia/gk20a/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gk20a/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gk20a/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gk20a/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gk20a/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gk20a/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gk20a/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/gk20a/sw_nonctx.bin");
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#endif
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static int
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gk20a_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
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{
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struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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if (nvkm_firmware_load_blob(subdev, "", "fecs_inst", ver,
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&gr->fecs.inst) ||
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nvkm_firmware_load_blob(subdev, "", "fecs_data", ver,
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&gr->fecs.data) ||
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nvkm_firmware_load_blob(subdev, "", "gpccs_inst", ver,
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&gr->gpccs.inst) ||
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nvkm_firmware_load_blob(subdev, "", "gpccs_data", ver,
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&gr->gpccs.data))
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return -ENOENT;
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gr->firmware = true;
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return gk20a_gr_load_sw(gr, "", ver);
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}
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static const struct gf100_gr_fwif
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gk20a_gr_fwif[] = {
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{ 0, gk20a_gr_load, &gk20a_gr },
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{}
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};
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int
|
||
|
|
gk20a_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
|
||
|
|
{
|
||
|
|
return gf100_gr_new_(gk20a_gr_fwif, device, type, inst, pgr);
|
||
|
|
}
|