449 lines
12 KiB
C
449 lines
12 KiB
C
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/*
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* Copyright 2018 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "nv50.h"
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#include "head.h"
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#include "ior.h"
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#include "channv50.h"
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#include "rootnv50.h"
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#include <core/gpuobj.h>
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#include <subdev/timer.h>
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int
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gv100_disp_wndw_cnt(struct nvkm_disp *disp, unsigned long *pmask)
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{
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struct nvkm_device *device = disp->engine.subdev.device;
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*pmask = nvkm_rd32(device, 0x610064);
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return (nvkm_rd32(device, 0x610074) & 0x03f00000) >> 20;
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}
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void
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gv100_disp_super(struct work_struct *work)
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{
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struct nv50_disp *disp =
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container_of(work, struct nv50_disp, supervisor);
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struct nvkm_subdev *subdev = &disp->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_head *head;
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u32 stat = nvkm_rd32(device, 0x6107a8);
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u32 mask[4];
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nvkm_debug(subdev, "supervisor %d: %08x\n", ffs(disp->super), stat);
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list_for_each_entry(head, &disp->base.head, head) {
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mask[head->id] = nvkm_rd32(device, 0x6107ac + (head->id * 4));
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HEAD_DBG(head, "%08x", mask[head->id]);
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}
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if (disp->super & 0x00000001) {
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nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG);
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nv50_disp_super_1(disp);
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list_for_each_entry(head, &disp->base.head, head) {
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if (!(mask[head->id] & 0x00001000))
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continue;
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nv50_disp_super_1_0(disp, head);
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}
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} else
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if (disp->super & 0x00000002) {
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list_for_each_entry(head, &disp->base.head, head) {
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if (!(mask[head->id] & 0x00001000))
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continue;
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nv50_disp_super_2_0(disp, head);
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}
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nvkm_outp_route(&disp->base);
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list_for_each_entry(head, &disp->base.head, head) {
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if (!(mask[head->id] & 0x00010000))
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continue;
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nv50_disp_super_2_1(disp, head);
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}
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list_for_each_entry(head, &disp->base.head, head) {
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if (!(mask[head->id] & 0x00001000))
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continue;
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nv50_disp_super_2_2(disp, head);
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}
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} else
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if (disp->super & 0x00000004) {
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list_for_each_entry(head, &disp->base.head, head) {
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if (!(mask[head->id] & 0x00001000))
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continue;
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nv50_disp_super_3_0(disp, head);
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}
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}
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list_for_each_entry(head, &disp->base.head, head)
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nvkm_wr32(device, 0x6107ac + (head->id * 4), 0x00000000);
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nvkm_wr32(device, 0x6107a8, 0x80000000);
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}
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static void
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gv100_disp_exception(struct nv50_disp *disp, int chid)
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{
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struct nvkm_subdev *subdev = &disp->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 stat = nvkm_rd32(device, 0x611020 + (chid * 12));
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u32 type = (stat & 0x00007000) >> 12;
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u32 mthd = (stat & 0x00000fff) << 2;
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const struct nvkm_enum *reason =
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nvkm_enum_find(nv50_disp_intr_error_type, type);
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/*TODO: Suspect 33->41 are for WRBK channel exceptions, but we
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* don't support those currently.
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*
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* CORE+WIN CHIDs map directly to the FE_EXCEPT() slots.
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*/
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if (chid <= 32) {
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u32 data = nvkm_rd32(device, 0x611024 + (chid * 12));
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u32 code = nvkm_rd32(device, 0x611028 + (chid * 12));
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nvkm_error(subdev, "chid %d stat %08x reason %d [%s] "
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"mthd %04x data %08x code %08x\n",
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chid, stat, type, reason ? reason->name : "",
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mthd, data, code);
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} else {
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nvkm_error(subdev, "chid %d stat %08x reason %d [%s] "
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"mthd %04x\n",
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chid, stat, type, reason ? reason->name : "", mthd);
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}
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if (chid < ARRAY_SIZE(disp->chan) && disp->chan[chid]) {
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switch (mthd) {
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case 0x0200:
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nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR);
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break;
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default:
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break;
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}
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}
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nvkm_wr32(device, 0x611020 + (chid * 12), 0x90000000);
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}
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static void
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gv100_disp_intr_ctrl_disp(struct nv50_disp *disp)
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{
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struct nvkm_subdev *subdev = &disp->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 stat = nvkm_rd32(device, 0x611c30);
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if (stat & 0x00000007) {
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disp->super = (stat & 0x00000007);
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queue_work(disp->wq, &disp->supervisor);
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nvkm_wr32(device, 0x611860, disp->super);
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stat &= ~0x00000007;
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}
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/*TODO: I would guess this is VBIOS_RELEASE, however, NFI how to
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* ACK it, nor does RM appear to bother.
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*/
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if (stat & 0x00000008)
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stat &= ~0x00000008;
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if (stat & 0x00000080) {
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u32 error = nvkm_mask(device, 0x611848, 0x00000000, 0x00000000);
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nvkm_warn(subdev, "error %08x\n", error);
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stat &= ~0x00000080;
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}
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if (stat & 0x00000100) {
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unsigned long wndws = nvkm_rd32(device, 0x611858);
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unsigned long other = nvkm_rd32(device, 0x61185c);
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int wndw;
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nvkm_wr32(device, 0x611858, wndws);
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nvkm_wr32(device, 0x61185c, other);
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/* AWAKEN_OTHER_CORE. */
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if (other & 0x00000001)
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nv50_disp_chan_uevent_send(disp, 0);
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/* AWAKEN_WIN_CH(n). */
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for_each_set_bit(wndw, &wndws, disp->wndw.nr) {
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nv50_disp_chan_uevent_send(disp, 1 + wndw);
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}
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}
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if (stat)
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nvkm_warn(subdev, "ctrl %08x\n", stat);
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}
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static void
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gv100_disp_intr_exc_other(struct nv50_disp *disp)
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{
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struct nvkm_subdev *subdev = &disp->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 stat = nvkm_rd32(device, 0x611854);
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unsigned long mask;
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int head;
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if (stat & 0x00000001) {
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nvkm_wr32(device, 0x611854, 0x00000001);
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gv100_disp_exception(disp, 0);
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stat &= ~0x00000001;
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}
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if ((mask = (stat & 0x00ff0000) >> 16)) {
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for_each_set_bit(head, &mask, disp->wndw.nr) {
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nvkm_wr32(device, 0x611854, 0x00010000 << head);
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gv100_disp_exception(disp, 73 + head);
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stat &= ~(0x00010000 << head);
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}
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}
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if (stat) {
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nvkm_warn(subdev, "exception %08x\n", stat);
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nvkm_wr32(device, 0x611854, stat);
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}
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}
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static void
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gv100_disp_intr_exc_winim(struct nv50_disp *disp)
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{
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struct nvkm_subdev *subdev = &disp->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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unsigned long stat = nvkm_rd32(device, 0x611850);
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int wndw;
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for_each_set_bit(wndw, &stat, disp->wndw.nr) {
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nvkm_wr32(device, 0x611850, BIT(wndw));
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gv100_disp_exception(disp, 33 + wndw);
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stat &= ~BIT(wndw);
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}
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if (stat) {
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nvkm_warn(subdev, "wimm %08x\n", (u32)stat);
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nvkm_wr32(device, 0x611850, stat);
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}
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}
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static void
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gv100_disp_intr_exc_win(struct nv50_disp *disp)
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{
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struct nvkm_subdev *subdev = &disp->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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unsigned long stat = nvkm_rd32(device, 0x61184c);
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int wndw;
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for_each_set_bit(wndw, &stat, disp->wndw.nr) {
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nvkm_wr32(device, 0x61184c, BIT(wndw));
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gv100_disp_exception(disp, 1 + wndw);
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stat &= ~BIT(wndw);
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}
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if (stat) {
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nvkm_warn(subdev, "wndw %08x\n", (u32)stat);
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nvkm_wr32(device, 0x61184c, stat);
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}
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}
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static void
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gv100_disp_intr_head_timing(struct nv50_disp *disp, int head)
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{
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struct nvkm_subdev *subdev = &disp->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 stat = nvkm_rd32(device, 0x611800 + (head * 0x04));
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/* LAST_DATA, LOADV. */
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if (stat & 0x00000003) {
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nvkm_wr32(device, 0x611800 + (head * 0x04), stat & 0x00000003);
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stat &= ~0x00000003;
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}
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if (stat & 0x00000004) {
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nvkm_disp_vblank(&disp->base, head);
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nvkm_wr32(device, 0x611800 + (head * 0x04), 0x00000004);
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stat &= ~0x00000004;
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}
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if (stat) {
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nvkm_warn(subdev, "head %08x\n", stat);
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nvkm_wr32(device, 0x611800 + (head * 0x04), stat);
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}
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}
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void
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gv100_disp_intr(struct nv50_disp *disp)
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{
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struct nvkm_subdev *subdev = &disp->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 stat = nvkm_rd32(device, 0x611ec0);
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unsigned long mask;
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int head;
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if ((mask = (stat & 0x000000ff))) {
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for_each_set_bit(head, &mask, 8) {
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gv100_disp_intr_head_timing(disp, head);
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stat &= ~BIT(head);
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}
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}
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if (stat & 0x00000200) {
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gv100_disp_intr_exc_win(disp);
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stat &= ~0x00000200;
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}
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if (stat & 0x00000400) {
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gv100_disp_intr_exc_winim(disp);
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stat &= ~0x00000400;
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}
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if (stat & 0x00000800) {
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gv100_disp_intr_exc_other(disp);
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stat &= ~0x00000800;
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}
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if (stat & 0x00001000) {
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gv100_disp_intr_ctrl_disp(disp);
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stat &= ~0x00001000;
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}
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if (stat)
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nvkm_warn(subdev, "intr %08x\n", stat);
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}
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void
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gv100_disp_fini(struct nv50_disp *disp)
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{
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struct nvkm_device *device = disp->base.engine.subdev.device;
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nvkm_wr32(device, 0x611db0, 0x00000000);
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}
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static int
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gv100_disp_init(struct nv50_disp *disp)
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{
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struct nvkm_device *device = disp->base.engine.subdev.device;
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struct nvkm_head *head;
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int i, j;
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u32 tmp;
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/* Claim ownership of display. */
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if (nvkm_rd32(device, 0x6254e8) & 0x00000002) {
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nvkm_mask(device, 0x6254e8, 0x00000001, 0x00000000);
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if (nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x6254e8) & 0x00000002))
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break;
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) < 0)
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return -EBUSY;
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}
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/* Lock pin capabilities. */
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tmp = nvkm_rd32(device, 0x610068);
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nvkm_wr32(device, 0x640008, tmp);
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/* SOR capabilities. */
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for (i = 0; i < disp->sor.nr; i++) {
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tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
|
||
|
|
nvkm_mask(device, 0x640000, 0x00000100 << i, 0x00000100 << i);
|
||
|
|
nvkm_wr32(device, 0x640144 + (i * 0x08), tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Head capabilities. */
|
||
|
|
list_for_each_entry(head, &disp->base.head, head) {
|
||
|
|
const int id = head->id;
|
||
|
|
|
||
|
|
/* RG. */
|
||
|
|
tmp = nvkm_rd32(device, 0x616300 + (id * 0x800));
|
||
|
|
nvkm_wr32(device, 0x640048 + (id * 0x020), tmp);
|
||
|
|
|
||
|
|
/* POSTCOMP. */
|
||
|
|
for (j = 0; j < 6 * 4; j += 4) {
|
||
|
|
tmp = nvkm_rd32(device, 0x616100 + (id * 0x800) + j);
|
||
|
|
nvkm_wr32(device, 0x640030 + (id * 0x20) + j, tmp);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Window capabilities. */
|
||
|
|
for (i = 0; i < disp->wndw.nr; i++) {
|
||
|
|
nvkm_mask(device, 0x640004, 1 << i, 1 << i);
|
||
|
|
for (j = 0; j < 6 * 4; j += 4) {
|
||
|
|
tmp = nvkm_rd32(device, 0x630050 + (i * 0x800) + j);
|
||
|
|
nvkm_wr32(device, 0x6401e4 + (i * 0x20) + j, tmp);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* IHUB capabilities. */
|
||
|
|
for (i = 0; i < 4; i++) {
|
||
|
|
tmp = nvkm_rd32(device, 0x62e000 + (i * 0x04));
|
||
|
|
nvkm_wr32(device, 0x640010 + (i * 0x04), tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
nvkm_mask(device, 0x610078, 0x00000001, 0x00000001);
|
||
|
|
|
||
|
|
/* Setup instance memory. */
|
||
|
|
switch (nvkm_memory_target(disp->inst->memory)) {
|
||
|
|
case NVKM_MEM_TARGET_VRAM: tmp = 0x00000001; break;
|
||
|
|
case NVKM_MEM_TARGET_NCOH: tmp = 0x00000002; break;
|
||
|
|
case NVKM_MEM_TARGET_HOST: tmp = 0x00000003; break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
nvkm_wr32(device, 0x610010, 0x00000008 | tmp);
|
||
|
|
nvkm_wr32(device, 0x610014, disp->inst->addr >> 16);
|
||
|
|
|
||
|
|
/* CTRL_DISP: AWAKEN, ERROR, SUPERVISOR[1-3]. */
|
||
|
|
nvkm_wr32(device, 0x611cf0, 0x00000187); /* MSK. */
|
||
|
|
nvkm_wr32(device, 0x611db0, 0x00000187); /* EN. */
|
||
|
|
|
||
|
|
/* EXC_OTHER: CURSn, CORE. */
|
||
|
|
nvkm_wr32(device, 0x611cec, disp->head.mask << 16 |
|
||
|
|
0x00000001); /* MSK. */
|
||
|
|
nvkm_wr32(device, 0x611dac, 0x00000000); /* EN. */
|
||
|
|
|
||
|
|
/* EXC_WINIM. */
|
||
|
|
nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */
|
||
|
|
nvkm_wr32(device, 0x611da8, 0x00000000); /* EN. */
|
||
|
|
|
||
|
|
/* EXC_WIN. */
|
||
|
|
nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */
|
||
|
|
nvkm_wr32(device, 0x611da4, 0x00000000); /* EN. */
|
||
|
|
|
||
|
|
/* HEAD_TIMING(n): VBLANK. */
|
||
|
|
list_for_each_entry(head, &disp->base.head, head) {
|
||
|
|
const u32 hoff = head->id * 4;
|
||
|
|
nvkm_wr32(device, 0x611cc0 + hoff, 0x00000004); /* MSK. */
|
||
|
|
nvkm_wr32(device, 0x611d80 + hoff, 0x00000000); /* EN. */
|
||
|
|
}
|
||
|
|
|
||
|
|
/* OR. */
|
||
|
|
nvkm_wr32(device, 0x611cf4, 0x00000000); /* MSK. */
|
||
|
|
nvkm_wr32(device, 0x611db4, 0x00000000); /* EN. */
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct nv50_disp_func
|
||
|
|
gv100_disp = {
|
||
|
|
.init = gv100_disp_init,
|
||
|
|
.fini = gv100_disp_fini,
|
||
|
|
.intr = gv100_disp_intr,
|
||
|
|
.uevent = &gv100_disp_chan_uevent,
|
||
|
|
.super = gv100_disp_super,
|
||
|
|
.root = &gv100_disp_root_oclass,
|
||
|
|
.wndw = { .cnt = gv100_disp_wndw_cnt },
|
||
|
|
.head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
|
||
|
|
.sor = { .cnt = gv100_sor_cnt, .new = gv100_sor_new },
|
||
|
|
.ramht_size = 0x2000,
|
||
|
|
};
|
||
|
|
|
||
|
|
int
|
||
|
|
gv100_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
|
||
|
|
struct nvkm_disp **pdisp)
|
||
|
|
{
|
||
|
|
return nv50_disp_new_(&gv100_disp, device, type, inst, pdisp);
|
||
|
|
}
|