112 lines
6.0 KiB
C
112 lines
6.0 KiB
C
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/* SPDX-License-Identifier: MIT */
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#ifndef __NVKM_DISP_DP_H__
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#define __NVKM_DISP_DP_H__
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#define nvkm_dp(p) container_of((p), struct nvkm_dp, outp)
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#include "outp.h"
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#include <core/notify.h>
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#include <subdev/bios.h>
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#include <subdev/bios/dp.h>
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struct nvkm_dp {
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union {
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struct nvkm_outp base;
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struct nvkm_outp outp;
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};
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struct nvbios_dpout info;
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u8 version;
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struct nvkm_i2c_aux *aux;
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struct nvkm_notify hpd;
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bool present;
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u8 dpcd[16];
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struct mutex mutex;
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struct {
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atomic_t done;
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bool mst;
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} lt;
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};
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int nvkm_dp_new(struct nvkm_disp *, int index, struct dcb_output *,
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struct nvkm_outp **);
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void nvkm_dp_disable(struct nvkm_outp *, struct nvkm_ior *);
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/* DPCD Receiver Capabilities */
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#define DPCD_RC00_DPCD_REV 0x00000
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#define DPCD_RC01_MAX_LINK_RATE 0x00001
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#define DPCD_RC02 0x00002
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#define DPCD_RC02_ENHANCED_FRAME_CAP 0x80
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#define DPCD_RC02_TPS3_SUPPORTED 0x40
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#define DPCD_RC02_MAX_LANE_COUNT 0x1f
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#define DPCD_RC03 0x00003
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#define DPCD_RC03_MAX_DOWNSPREAD 0x01
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#define DPCD_RC0E_AUX_RD_INTERVAL 0x0000e
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/* DPCD Link Configuration */
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#define DPCD_LC00_LINK_BW_SET 0x00100
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#define DPCD_LC01 0x00101
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#define DPCD_LC01_ENHANCED_FRAME_EN 0x80
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#define DPCD_LC01_LANE_COUNT_SET 0x1f
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#define DPCD_LC02 0x00102
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#define DPCD_LC02_TRAINING_PATTERN_SET 0x03
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#define DPCD_LC03(l) ((l) + 0x00103)
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#define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED 0x20
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#define DPCD_LC03_PRE_EMPHASIS_SET 0x18
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#define DPCD_LC03_MAX_SWING_REACHED 0x04
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#define DPCD_LC03_VOLTAGE_SWING_SET 0x03
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#define DPCD_LC0F 0x0010f
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#define DPCD_LC0F_LANE1_MAX_POST_CURSOR2_REACHED 0x40
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#define DPCD_LC0F_LANE1_POST_CURSOR2_SET 0x30
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#define DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED 0x04
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#define DPCD_LC0F_LANE0_POST_CURSOR2_SET 0x03
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#define DPCD_LC10 0x00110
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#define DPCD_LC10_LANE3_MAX_POST_CURSOR2_REACHED 0x40
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#define DPCD_LC10_LANE3_POST_CURSOR2_SET 0x30
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#define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED 0x04
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#define DPCD_LC10_LANE2_POST_CURSOR2_SET 0x03
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/* DPCD Link/Sink Status */
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#define DPCD_LS02 0x00202
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#define DPCD_LS02_LANE1_SYMBOL_LOCKED 0x40
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#define DPCD_LS02_LANE1_CHANNEL_EQ_DONE 0x20
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#define DPCD_LS02_LANE1_CR_DONE 0x10
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#define DPCD_LS02_LANE0_SYMBOL_LOCKED 0x04
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#define DPCD_LS02_LANE0_CHANNEL_EQ_DONE 0x02
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#define DPCD_LS02_LANE0_CR_DONE 0x01
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#define DPCD_LS03 0x00203
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#define DPCD_LS03_LANE3_SYMBOL_LOCKED 0x40
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#define DPCD_LS03_LANE3_CHANNEL_EQ_DONE 0x20
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#define DPCD_LS03_LANE3_CR_DONE 0x10
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#define DPCD_LS03_LANE2_SYMBOL_LOCKED 0x04
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#define DPCD_LS03_LANE2_CHANNEL_EQ_DONE 0x02
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#define DPCD_LS03_LANE2_CR_DONE 0x01
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#define DPCD_LS04 0x00204
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#define DPCD_LS04_LINK_STATUS_UPDATED 0x80
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#define DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED 0x40
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#define DPCD_LS04_INTERLANE_ALIGN_DONE 0x01
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#define DPCD_LS06 0x00206
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#define DPCD_LS06_LANE1_PRE_EMPHASIS 0xc0
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#define DPCD_LS06_LANE1_VOLTAGE_SWING 0x30
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#define DPCD_LS06_LANE0_PRE_EMPHASIS 0x0c
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#define DPCD_LS06_LANE0_VOLTAGE_SWING 0x03
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#define DPCD_LS07 0x00207
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#define DPCD_LS07_LANE3_PRE_EMPHASIS 0xc0
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#define DPCD_LS07_LANE3_VOLTAGE_SWING 0x30
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#define DPCD_LS07_LANE2_PRE_EMPHASIS 0x0c
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#define DPCD_LS07_LANE2_VOLTAGE_SWING 0x03
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#define DPCD_LS0C 0x0020c
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#define DPCD_LS0C_LANE3_POST_CURSOR2 0xc0
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#define DPCD_LS0C_LANE2_POST_CURSOR2 0x30
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#define DPCD_LS0C_LANE1_POST_CURSOR2 0x0c
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#define DPCD_LS0C_LANE0_POST_CURSOR2 0x03
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/* DPCD Sink Control */
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#define DPCD_SC00 0x00600
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#define DPCD_SC00_SET_POWER 0x03
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#define DPCD_SC00_SET_POWER_D0 0x01
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#define DPCD_SC00_SET_POWER_D3 0x03
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#endif
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