64 lines
1.6 KiB
C
64 lines
1.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2013-2016 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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#ifndef __MSM_FENCE_H__
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#define __MSM_FENCE_H__
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#include "msm_drv.h"
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/**
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* struct msm_fence_context - fence context for gpu
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*
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* Each ringbuffer has a single fence context, with the GPU writing an
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* incrementing fence seqno at the end of each submit
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*/
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struct msm_fence_context {
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struct drm_device *dev;
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/** name: human readable name for fence timeline */
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char name[32];
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/** context: see dma_fence_context_alloc() */
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unsigned context;
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/**
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* last_fence:
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*
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* Last assigned fence, incremented each time a fence is created
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* on this fence context. If last_fence == completed_fence,
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* there is no remaining pending work
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*/
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uint32_t last_fence;
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/**
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* completed_fence:
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*
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* The last completed fence, updated from the CPU after interrupt
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* from GPU
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*/
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uint32_t completed_fence;
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/**
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* fenceptr:
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*
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* The address that the GPU directly writes with completed fence
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* seqno. This can be ahead of completed_fence. We can peek at
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* this to see if a fence has already signaled but the CPU hasn't
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* gotten around to handling the irq and updating completed_fence
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*/
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volatile uint32_t *fenceptr;
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spinlock_t spinlock;
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};
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struct msm_fence_context * msm_fence_context_alloc(struct drm_device *dev,
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volatile uint32_t *fenceptr, const char *name);
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void msm_fence_context_free(struct msm_fence_context *fctx);
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void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence);
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struct dma_fence * msm_fence_alloc(struct msm_fence_context *fctx);
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#endif
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