459 lines
11 KiB
C
459 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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*/
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#include <linux/bitops.h>
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#include <linux/slab.h>
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#include "dpu_kms.h"
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#include "dpu_hw_interrupts.h"
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#include "dpu_hw_util.h"
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#include "dpu_hw_mdss.h"
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/**
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* Register offsets in MDSS register file for the interrupt registers
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* w.r.t. the MDP base
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*/
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#define MDP_SSPP_TOP0_OFF 0x0
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#define MDP_INTF_0_OFF 0x6A000
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#define MDP_INTF_1_OFF 0x6A800
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#define MDP_INTF_2_OFF 0x6B000
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#define MDP_INTF_3_OFF 0x6B800
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#define MDP_INTF_4_OFF 0x6C000
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#define MDP_INTF_5_OFF 0x6C800
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#define INTF_INTR_EN 0x1c0
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#define INTF_INTR_STATUS 0x1c4
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#define INTF_INTR_CLEAR 0x1c8
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#define MDP_AD4_0_OFF 0x7C000
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#define MDP_AD4_1_OFF 0x7D000
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#define MDP_AD4_INTR_EN_OFF 0x41c
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#define MDP_AD4_INTR_CLEAR_OFF 0x424
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#define MDP_AD4_INTR_STATUS_OFF 0x420
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#define MDP_INTF_0_OFF_REV_7xxx 0x34000
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#define MDP_INTF_1_OFF_REV_7xxx 0x35000
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#define MDP_INTF_5_OFF_REV_7xxx 0x39000
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/**
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* struct dpu_intr_reg - array of DPU register sets
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* @clr_off: offset to CLEAR reg
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* @en_off: offset to ENABLE reg
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* @status_off: offset to STATUS reg
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*/
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struct dpu_intr_reg {
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u32 clr_off;
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u32 en_off;
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u32 status_off;
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};
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/*
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* struct dpu_intr_reg - List of DPU interrupt registers
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*
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* When making changes be sure to sync with dpu_hw_intr_reg
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*/
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static const struct dpu_intr_reg dpu_intr_set[] = {
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{
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MDP_SSPP_TOP0_OFF+INTR_CLEAR,
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MDP_SSPP_TOP0_OFF+INTR_EN,
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MDP_SSPP_TOP0_OFF+INTR_STATUS
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},
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{
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MDP_SSPP_TOP0_OFF+INTR2_CLEAR,
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MDP_SSPP_TOP0_OFF+INTR2_EN,
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MDP_SSPP_TOP0_OFF+INTR2_STATUS
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},
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{
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MDP_SSPP_TOP0_OFF+HIST_INTR_CLEAR,
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MDP_SSPP_TOP0_OFF+HIST_INTR_EN,
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MDP_SSPP_TOP0_OFF+HIST_INTR_STATUS
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},
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{
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MDP_INTF_0_OFF+INTF_INTR_CLEAR,
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MDP_INTF_0_OFF+INTF_INTR_EN,
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MDP_INTF_0_OFF+INTF_INTR_STATUS
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},
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{
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MDP_INTF_1_OFF+INTF_INTR_CLEAR,
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MDP_INTF_1_OFF+INTF_INTR_EN,
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MDP_INTF_1_OFF+INTF_INTR_STATUS
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},
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{
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MDP_INTF_2_OFF+INTF_INTR_CLEAR,
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MDP_INTF_2_OFF+INTF_INTR_EN,
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MDP_INTF_2_OFF+INTF_INTR_STATUS
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},
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{
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MDP_INTF_3_OFF+INTF_INTR_CLEAR,
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MDP_INTF_3_OFF+INTF_INTR_EN,
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MDP_INTF_3_OFF+INTF_INTR_STATUS
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},
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{
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MDP_INTF_4_OFF+INTF_INTR_CLEAR,
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MDP_INTF_4_OFF+INTF_INTR_EN,
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MDP_INTF_4_OFF+INTF_INTR_STATUS
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},
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{
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MDP_INTF_5_OFF+INTF_INTR_CLEAR,
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MDP_INTF_5_OFF+INTF_INTR_EN,
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MDP_INTF_5_OFF+INTF_INTR_STATUS
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},
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{
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MDP_AD4_0_OFF + MDP_AD4_INTR_CLEAR_OFF,
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MDP_AD4_0_OFF + MDP_AD4_INTR_EN_OFF,
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MDP_AD4_0_OFF + MDP_AD4_INTR_STATUS_OFF,
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},
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{
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MDP_AD4_1_OFF + MDP_AD4_INTR_CLEAR_OFF,
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MDP_AD4_1_OFF + MDP_AD4_INTR_EN_OFF,
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MDP_AD4_1_OFF + MDP_AD4_INTR_STATUS_OFF,
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},
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{
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MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_CLEAR,
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MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_EN,
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MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_STATUS
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},
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{
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MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_CLEAR,
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MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_EN,
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MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_STATUS
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},
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{
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MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_CLEAR,
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MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN,
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MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_STATUS
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},
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};
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#define DPU_IRQ_REG(irq_idx) (irq_idx / 32)
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#define DPU_IRQ_MASK(irq_idx) (BIT(irq_idx % 32))
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static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
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int irq_idx)
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{
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int reg_idx;
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if (!intr)
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return;
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reg_idx = DPU_IRQ_REG(irq_idx);
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DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, DPU_IRQ_MASK(irq_idx));
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/* ensure register writes go through */
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wmb();
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}
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static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
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void (*cbfunc)(void *, int),
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void *arg)
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{
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int reg_idx;
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int irq_idx;
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u32 irq_status;
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u32 enable_mask;
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int bit;
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unsigned long irq_flags;
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if (!intr)
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return;
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/*
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* The dispatcher will save the IRQ status before calling here.
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* Now need to go through each IRQ status and find matching
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* irq lookup index.
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*/
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spin_lock_irqsave(&intr->irq_lock, irq_flags);
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for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
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if (!test_bit(reg_idx, &intr->irq_mask))
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continue;
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/* Read interrupt status */
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irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
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/* Read enable mask */
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enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
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/* and clear the interrupt */
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if (irq_status)
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DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
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irq_status);
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/* Finally update IRQ status based on enable mask */
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irq_status &= enable_mask;
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if (!irq_status)
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continue;
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/*
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* Search through matching intr status.
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*/
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while ((bit = ffs(irq_status)) != 0) {
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irq_idx = DPU_IRQ_IDX(reg_idx, bit - 1);
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/*
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* Once a match on irq mask, perform a callback
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* to the given cbfunc. cbfunc will take care
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* the interrupt status clearing. If cbfunc is
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* not provided, then the interrupt clearing
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* is here.
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*/
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if (cbfunc)
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cbfunc(arg, irq_idx);
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dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
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/*
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* When callback finish, clear the irq_status
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* with the matching mask. Once irq_status
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* is all cleared, the search can be stopped.
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*/
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irq_status &= ~BIT(bit - 1);
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}
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}
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/* ensure register writes go through */
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wmb();
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spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
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}
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static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
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{
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int reg_idx;
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const struct dpu_intr_reg *reg;
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const char *dbgstr = NULL;
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uint32_t cache_irq_mask;
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if (!intr)
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return -EINVAL;
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if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
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pr_err("invalid IRQ index: [%d]\n", irq_idx);
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return -EINVAL;
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}
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/*
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* The cache_irq_mask and hardware RMW operations needs to be done
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* under irq_lock and it's the caller's responsibility to ensure that's
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* held.
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*/
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assert_spin_locked(&intr->irq_lock);
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reg_idx = DPU_IRQ_REG(irq_idx);
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reg = &dpu_intr_set[reg_idx];
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cache_irq_mask = intr->cache_irq_mask[reg_idx];
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if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
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dbgstr = "DPU IRQ already set:";
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} else {
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dbgstr = "DPU IRQ enabled:";
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cache_irq_mask |= DPU_IRQ_MASK(irq_idx);
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/* Cleaning any pending interrupt */
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DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
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/* Enabling interrupts with the new mask */
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DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
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/* ensure register write goes through */
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wmb();
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intr->cache_irq_mask[reg_idx] = cache_irq_mask;
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}
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pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr,
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DPU_IRQ_MASK(irq_idx), cache_irq_mask);
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return 0;
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}
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static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
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{
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int reg_idx;
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const struct dpu_intr_reg *reg;
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const char *dbgstr = NULL;
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uint32_t cache_irq_mask;
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if (!intr)
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return -EINVAL;
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if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
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pr_err("invalid IRQ index: [%d]\n", irq_idx);
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return -EINVAL;
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}
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/*
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* The cache_irq_mask and hardware RMW operations needs to be done
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* under irq_lock and it's the caller's responsibility to ensure that's
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* held.
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*/
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assert_spin_locked(&intr->irq_lock);
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reg_idx = DPU_IRQ_REG(irq_idx);
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reg = &dpu_intr_set[reg_idx];
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cache_irq_mask = intr->cache_irq_mask[reg_idx];
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if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
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dbgstr = "DPU IRQ is already cleared:";
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} else {
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dbgstr = "DPU IRQ mask disable:";
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cache_irq_mask &= ~DPU_IRQ_MASK(irq_idx);
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/* Disable interrupts based on the new mask */
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DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
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/* Cleaning any pending interrupt */
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DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
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/* ensure register write goes through */
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wmb();
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intr->cache_irq_mask[reg_idx] = cache_irq_mask;
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}
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pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr,
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DPU_IRQ_MASK(irq_idx), cache_irq_mask);
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return 0;
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}
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static int dpu_hw_intr_clear_irqs(struct dpu_hw_intr *intr)
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{
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int i;
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if (!intr)
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
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if (test_bit(i, &intr->irq_mask))
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DPU_REG_WRITE(&intr->hw,
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dpu_intr_set[i].clr_off, 0xffffffff);
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}
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/* ensure register writes go through */
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wmb();
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return 0;
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}
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static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr)
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{
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int i;
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if (!intr)
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
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if (test_bit(i, &intr->irq_mask))
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DPU_REG_WRITE(&intr->hw,
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dpu_intr_set[i].en_off, 0x00000000);
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}
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/* ensure register writes go through */
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wmb();
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return 0;
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}
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static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
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int irq_idx, bool clear)
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{
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int reg_idx;
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unsigned long irq_flags;
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u32 intr_status;
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if (!intr)
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return 0;
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||
|
|
if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
|
||
|
|
pr_err("invalid IRQ index: [%d]\n", irq_idx);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
spin_lock_irqsave(&intr->irq_lock, irq_flags);
|
||
|
|
|
||
|
|
reg_idx = DPU_IRQ_REG(irq_idx);
|
||
|
|
intr_status = DPU_REG_READ(&intr->hw,
|
||
|
|
dpu_intr_set[reg_idx].status_off) &
|
||
|
|
DPU_IRQ_MASK(irq_idx);
|
||
|
|
if (intr_status && clear)
|
||
|
|
DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
|
||
|
|
intr_status);
|
||
|
|
|
||
|
|
/* ensure register writes go through */
|
||
|
|
wmb();
|
||
|
|
|
||
|
|
spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
|
||
|
|
|
||
|
|
return intr_status;
|
||
|
|
}
|
||
|
|
|
||
|
|
static unsigned long dpu_hw_intr_lock(struct dpu_hw_intr *intr)
|
||
|
|
{
|
||
|
|
unsigned long irq_flags;
|
||
|
|
|
||
|
|
spin_lock_irqsave(&intr->irq_lock, irq_flags);
|
||
|
|
|
||
|
|
return irq_flags;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void dpu_hw_intr_unlock(struct dpu_hw_intr *intr, unsigned long irq_flags)
|
||
|
|
{
|
||
|
|
spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __setup_intr_ops(struct dpu_hw_intr_ops *ops)
|
||
|
|
{
|
||
|
|
ops->enable_irq_locked = dpu_hw_intr_enable_irq_locked;
|
||
|
|
ops->disable_irq_locked = dpu_hw_intr_disable_irq_locked;
|
||
|
|
ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
|
||
|
|
ops->clear_all_irqs = dpu_hw_intr_clear_irqs;
|
||
|
|
ops->disable_all_irqs = dpu_hw_intr_disable_irqs;
|
||
|
|
ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status;
|
||
|
|
ops->lock = dpu_hw_intr_lock;
|
||
|
|
ops->unlock = dpu_hw_intr_unlock;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __intr_offset(struct dpu_mdss_cfg *m,
|
||
|
|
void __iomem *addr, struct dpu_hw_blk_reg_map *hw)
|
||
|
|
{
|
||
|
|
hw->base_off = addr;
|
||
|
|
hw->blk_off = m->mdp[0].base;
|
||
|
|
hw->hwversion = m->hwversion;
|
||
|
|
}
|
||
|
|
|
||
|
|
struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
|
||
|
|
struct dpu_mdss_cfg *m)
|
||
|
|
{
|
||
|
|
struct dpu_hw_intr *intr;
|
||
|
|
|
||
|
|
if (!addr || !m)
|
||
|
|
return ERR_PTR(-EINVAL);
|
||
|
|
|
||
|
|
intr = kzalloc(sizeof(*intr), GFP_KERNEL);
|
||
|
|
if (!intr)
|
||
|
|
return ERR_PTR(-ENOMEM);
|
||
|
|
|
||
|
|
__intr_offset(m, addr, &intr->hw);
|
||
|
|
__setup_intr_ops(&intr->ops);
|
||
|
|
|
||
|
|
intr->total_irqs = ARRAY_SIZE(dpu_intr_set) * 32;
|
||
|
|
|
||
|
|
intr->cache_irq_mask = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32),
|
||
|
|
GFP_KERNEL);
|
||
|
|
if (intr->cache_irq_mask == NULL) {
|
||
|
|
kfree(intr);
|
||
|
|
return ERR_PTR(-ENOMEM);
|
||
|
|
}
|
||
|
|
|
||
|
|
intr->irq_mask = m->mdss_irqs;
|
||
|
|
|
||
|
|
spin_lock_init(&intr->irq_lock);
|
||
|
|
|
||
|
|
return intr;
|
||
|
|
}
|
||
|
|
|
||
|
|
void dpu_hw_intr_destroy(struct dpu_hw_intr *intr)
|
||
|
|
{
|
||
|
|
if (intr) {
|
||
|
|
kfree(intr->cache_irq_mask);
|
||
|
|
kfree(intr);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|