627 lines
15 KiB
C
627 lines
15 KiB
C
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2021 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "intel_guc_slpc.h"
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#include "gt/intel_gt.h"
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static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
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{
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return container_of(slpc, struct intel_guc, slpc);
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}
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static inline struct intel_gt *slpc_to_gt(struct intel_guc_slpc *slpc)
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{
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return guc_to_gt(slpc_to_guc(slpc));
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}
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static inline struct drm_i915_private *slpc_to_i915(struct intel_guc_slpc *slpc)
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{
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return slpc_to_gt(slpc)->i915;
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}
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static bool __detect_slpc_supported(struct intel_guc *guc)
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{
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/* GuC SLPC is unavailable for pre-Gen12 */
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return guc->submission_supported &&
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GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12;
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}
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static bool __guc_slpc_selected(struct intel_guc *guc)
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{
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if (!intel_guc_slpc_is_supported(guc))
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return false;
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return guc->submission_selected;
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}
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void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
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{
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struct intel_guc *guc = slpc_to_guc(slpc);
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slpc->supported = __detect_slpc_supported(guc);
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slpc->selected = __guc_slpc_selected(guc);
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}
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static void slpc_mem_set_param(struct slpc_shared_data *data,
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u32 id, u32 value)
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{
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GEM_BUG_ON(id >= SLPC_MAX_OVERRIDE_PARAMETERS);
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/*
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* When the flag bit is set, corresponding value will be read
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* and applied by SLPC.
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*/
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data->override_params.bits[id >> 5] |= (1 << (id % 32));
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data->override_params.values[id] = value;
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}
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static void slpc_mem_set_enabled(struct slpc_shared_data *data,
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u8 enable_id, u8 disable_id)
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{
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/*
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* Enabling a param involves setting the enable_id
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* to 1 and disable_id to 0.
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*/
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slpc_mem_set_param(data, enable_id, 1);
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slpc_mem_set_param(data, disable_id, 0);
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}
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static void slpc_mem_set_disabled(struct slpc_shared_data *data,
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u8 enable_id, u8 disable_id)
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{
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/*
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* Disabling a param involves setting the enable_id
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* to 0 and disable_id to 1.
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*/
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slpc_mem_set_param(data, disable_id, 1);
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slpc_mem_set_param(data, enable_id, 0);
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}
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int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
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{
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struct intel_guc *guc = slpc_to_guc(slpc);
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struct drm_i915_private *i915 = slpc_to_i915(slpc);
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u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
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int err;
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GEM_BUG_ON(slpc->vma);
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err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void **)&slpc->vaddr);
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if (unlikely(err)) {
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drm_err(&i915->drm,
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"Failed to allocate SLPC struct (err=%pe)\n",
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ERR_PTR(err));
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return err;
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}
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slpc->max_freq_softlimit = 0;
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slpc->min_freq_softlimit = 0;
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return err;
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}
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static u32 slpc_get_state(struct intel_guc_slpc *slpc)
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{
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struct slpc_shared_data *data;
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GEM_BUG_ON(!slpc->vma);
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drm_clflush_virt_range(slpc->vaddr, sizeof(u32));
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data = slpc->vaddr;
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return data->header.global_state;
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}
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static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
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{
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u32 request[] = {
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GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
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SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2),
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id,
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value,
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};
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int ret;
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ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
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return ret > 0 ? -EPROTO : ret;
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}
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static int guc_action_slpc_unset_param(struct intel_guc *guc, u8 id)
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{
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u32 request[] = {
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GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
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SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1),
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id,
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};
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return intel_guc_send(guc, request, ARRAY_SIZE(request));
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}
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static bool slpc_is_running(struct intel_guc_slpc *slpc)
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{
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return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
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}
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static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)
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{
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u32 request[] = {
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GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
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SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
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offset,
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0,
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};
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int ret;
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ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
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return ret > 0 ? -EPROTO : ret;
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}
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static int slpc_query_task_state(struct intel_guc_slpc *slpc)
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{
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struct intel_guc *guc = slpc_to_guc(slpc);
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struct drm_i915_private *i915 = slpc_to_i915(slpc);
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u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
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int ret;
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ret = guc_action_slpc_query(guc, offset);
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if (unlikely(ret))
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drm_err(&i915->drm, "Failed to query task state (%pe)\n",
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ERR_PTR(ret));
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drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
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return ret;
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}
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static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
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{
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struct intel_guc *guc = slpc_to_guc(slpc);
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struct drm_i915_private *i915 = slpc_to_i915(slpc);
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int ret;
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GEM_BUG_ON(id >= SLPC_MAX_PARAM);
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ret = guc_action_slpc_set_param(guc, id, value);
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if (ret)
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drm_err(&i915->drm, "Failed to set param %d to %u (%pe)\n",
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id, value, ERR_PTR(ret));
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return ret;
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}
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static int slpc_unset_param(struct intel_guc_slpc *slpc,
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u8 id)
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{
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struct intel_guc *guc = slpc_to_guc(slpc);
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GEM_BUG_ON(id >= SLPC_MAX_PARAM);
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return guc_action_slpc_unset_param(guc, id);
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}
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static const char *slpc_global_state_to_string(enum slpc_global_state state)
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{
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switch (state) {
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case SLPC_GLOBAL_STATE_NOT_RUNNING:
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return "not running";
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case SLPC_GLOBAL_STATE_INITIALIZING:
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return "initializing";
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case SLPC_GLOBAL_STATE_RESETTING:
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return "resetting";
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case SLPC_GLOBAL_STATE_RUNNING:
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return "running";
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case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
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return "shutting down";
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case SLPC_GLOBAL_STATE_ERROR:
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return "error";
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default:
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return "unknown";
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}
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}
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static const char *slpc_get_state_string(struct intel_guc_slpc *slpc)
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{
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return slpc_global_state_to_string(slpc_get_state(slpc));
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}
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static int guc_action_slpc_reset(struct intel_guc *guc, u32 offset)
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{
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u32 request[] = {
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GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
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SLPC_EVENT(SLPC_EVENT_RESET, 2),
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offset,
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0,
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};
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int ret;
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ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
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return ret > 0 ? -EPROTO : ret;
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}
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static int slpc_reset(struct intel_guc_slpc *slpc)
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{
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struct drm_i915_private *i915 = slpc_to_i915(slpc);
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struct intel_guc *guc = slpc_to_guc(slpc);
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u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
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int ret;
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ret = guc_action_slpc_reset(guc, offset);
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if (unlikely(ret < 0)) {
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drm_err(&i915->drm, "SLPC reset action failed (%pe)\n",
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ERR_PTR(ret));
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return ret;
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}
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if (!ret) {
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if (wait_for(slpc_is_running(slpc), SLPC_RESET_TIMEOUT_MS)) {
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drm_err(&i915->drm, "SLPC not enabled! State = %s\n",
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slpc_get_state_string(slpc));
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return -EIO;
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}
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}
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return 0;
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}
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static u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc)
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{
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struct slpc_shared_data *data = slpc->vaddr;
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GEM_BUG_ON(!slpc->vma);
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return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK,
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data->task_state_data.freq) *
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GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
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}
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static u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc)
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{
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struct slpc_shared_data *data = slpc->vaddr;
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GEM_BUG_ON(!slpc->vma);
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return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK,
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data->task_state_data.freq) *
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GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
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}
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static void slpc_shared_data_reset(struct slpc_shared_data *data)
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{
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memset(data, 0, sizeof(struct slpc_shared_data));
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data->header.size = sizeof(struct slpc_shared_data);
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/* Enable only GTPERF task, disable others */
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slpc_mem_set_enabled(data, SLPC_PARAM_TASK_ENABLE_GTPERF,
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SLPC_PARAM_TASK_DISABLE_GTPERF);
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slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_BALANCER,
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SLPC_PARAM_TASK_DISABLE_BALANCER);
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slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_DCC,
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SLPC_PARAM_TASK_DISABLE_DCC);
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}
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/**
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* intel_guc_slpc_set_max_freq() - Set max frequency limit for SLPC.
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* @slpc: pointer to intel_guc_slpc.
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* @val: frequency (MHz)
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*
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* This function will invoke GuC SLPC action to update the max frequency
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* limit for unslice.
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*
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* Return: 0 on success, non-zero error code on failure.
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*/
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int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
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{
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struct drm_i915_private *i915 = slpc_to_i915(slpc);
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intel_wakeref_t wakeref;
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int ret;
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if (val < slpc->min_freq ||
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val > slpc->rp0_freq ||
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val < slpc->min_freq_softlimit)
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return -EINVAL;
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with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
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ret = slpc_set_param(slpc,
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SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
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val);
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/* Return standardized err code for sysfs calls */
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if (ret)
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ret = -EIO;
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}
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if (!ret)
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slpc->max_freq_softlimit = val;
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return ret;
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}
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/**
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* intel_guc_slpc_get_max_freq() - Get max frequency limit for SLPC.
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* @slpc: pointer to intel_guc_slpc.
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* @val: pointer to val which will hold max frequency (MHz)
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*
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* This function will invoke GuC SLPC action to read the max frequency
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* limit for unslice.
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*
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* Return: 0 on success, non-zero error code on failure.
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*/
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int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val)
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{
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struct drm_i915_private *i915 = slpc_to_i915(slpc);
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intel_wakeref_t wakeref;
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int ret = 0;
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with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
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/* Force GuC to update task data */
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ret = slpc_query_task_state(slpc);
|
||
|
|
|
||
|
|
if (!ret)
|
||
|
|
*val = slpc_decode_max_freq(slpc);
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
|
||
|
|
* @slpc: pointer to intel_guc_slpc.
|
||
|
|
* @val: frequency (MHz)
|
||
|
|
*
|
||
|
|
* This function will invoke GuC SLPC action to update the min unslice
|
||
|
|
* frequency.
|
||
|
|
*
|
||
|
|
* Return: 0 on success, non-zero error code on failure.
|
||
|
|
*/
|
||
|
|
int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
|
||
|
|
{
|
||
|
|
struct drm_i915_private *i915 = slpc_to_i915(slpc);
|
||
|
|
intel_wakeref_t wakeref;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
if (val < slpc->min_freq ||
|
||
|
|
val > slpc->rp0_freq ||
|
||
|
|
val > slpc->max_freq_softlimit)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
|
||
|
|
ret = slpc_set_param(slpc,
|
||
|
|
SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
|
||
|
|
val);
|
||
|
|
|
||
|
|
/* Return standardized err code for sysfs calls */
|
||
|
|
if (ret)
|
||
|
|
ret = -EIO;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!ret)
|
||
|
|
slpc->min_freq_softlimit = val;
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* intel_guc_slpc_get_min_freq() - Get min frequency limit for SLPC.
|
||
|
|
* @slpc: pointer to intel_guc_slpc.
|
||
|
|
* @val: pointer to val which will hold min frequency (MHz)
|
||
|
|
*
|
||
|
|
* This function will invoke GuC SLPC action to read the min frequency
|
||
|
|
* limit for unslice.
|
||
|
|
*
|
||
|
|
* Return: 0 on success, non-zero error code on failure.
|
||
|
|
*/
|
||
|
|
int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val)
|
||
|
|
{
|
||
|
|
struct drm_i915_private *i915 = slpc_to_i915(slpc);
|
||
|
|
intel_wakeref_t wakeref;
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
|
||
|
|
/* Force GuC to update task data */
|
||
|
|
ret = slpc_query_task_state(slpc);
|
||
|
|
|
||
|
|
if (!ret)
|
||
|
|
*val = slpc_decode_min_freq(slpc);
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
|
||
|
|
{
|
||
|
|
u32 pm_intrmsk_mbz = 0;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Allow GuC to receive ARAT timer expiry event.
|
||
|
|
* This interrupt register is setup by RPS code
|
||
|
|
* when host based Turbo is enabled.
|
||
|
|
*/
|
||
|
|
pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
|
||
|
|
|
||
|
|
intel_uncore_rmw(gt->uncore,
|
||
|
|
GEN6_PMINTRMSK, pm_intrmsk_mbz, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
|
||
|
|
{
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Softlimits are initially equivalent to platform limits
|
||
|
|
* unless they have deviated from defaults, in which case,
|
||
|
|
* we retain the values and set min/max accordingly.
|
||
|
|
*/
|
||
|
|
if (!slpc->max_freq_softlimit)
|
||
|
|
slpc->max_freq_softlimit = slpc->rp0_freq;
|
||
|
|
else if (slpc->max_freq_softlimit != slpc->rp0_freq)
|
||
|
|
ret = intel_guc_slpc_set_max_freq(slpc,
|
||
|
|
slpc->max_freq_softlimit);
|
||
|
|
|
||
|
|
if (unlikely(ret))
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
if (!slpc->min_freq_softlimit)
|
||
|
|
slpc->min_freq_softlimit = slpc->min_freq;
|
||
|
|
else if (slpc->min_freq_softlimit != slpc->min_freq)
|
||
|
|
return intel_guc_slpc_set_min_freq(slpc,
|
||
|
|
slpc->min_freq_softlimit);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int slpc_ignore_eff_freq(struct intel_guc_slpc *slpc, bool ignore)
|
||
|
|
{
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
if (ignore) {
|
||
|
|
ret = slpc_set_param(slpc,
|
||
|
|
SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
|
||
|
|
ignore);
|
||
|
|
if (!ret)
|
||
|
|
return slpc_set_param(slpc,
|
||
|
|
SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
|
||
|
|
slpc->min_freq);
|
||
|
|
} else {
|
||
|
|
ret = slpc_unset_param(slpc,
|
||
|
|
SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY);
|
||
|
|
if (!ret)
|
||
|
|
return slpc_unset_param(slpc,
|
||
|
|
SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ);
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
|
||
|
|
{
|
||
|
|
/* Force SLPC to used platform rp0 */
|
||
|
|
return slpc_set_param(slpc,
|
||
|
|
SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
|
||
|
|
slpc->rp0_freq);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void slpc_get_rp_values(struct intel_guc_slpc *slpc)
|
||
|
|
{
|
||
|
|
u32 rp_state_cap;
|
||
|
|
|
||
|
|
rp_state_cap = intel_uncore_read(slpc_to_gt(slpc)->uncore,
|
||
|
|
GEN6_RP_STATE_CAP);
|
||
|
|
|
||
|
|
slpc->rp0_freq = REG_FIELD_GET(RP0_CAP_MASK, rp_state_cap) *
|
||
|
|
GT_FREQUENCY_MULTIPLIER;
|
||
|
|
slpc->rp1_freq = REG_FIELD_GET(RP1_CAP_MASK, rp_state_cap) *
|
||
|
|
GT_FREQUENCY_MULTIPLIER;
|
||
|
|
slpc->min_freq = REG_FIELD_GET(RPN_CAP_MASK, rp_state_cap) *
|
||
|
|
GT_FREQUENCY_MULTIPLIER;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* intel_guc_slpc_enable() - Start SLPC
|
||
|
|
* @slpc: pointer to intel_guc_slpc.
|
||
|
|
*
|
||
|
|
* SLPC is enabled by setting up the shared data structure and
|
||
|
|
* sending reset event to GuC SLPC. Initial data is setup in
|
||
|
|
* intel_guc_slpc_init. Here we send the reset event. We do
|
||
|
|
* not currently need a slpc_disable since this is taken care
|
||
|
|
* of automatically when a reset/suspend occurs and the GuC
|
||
|
|
* CTB is destroyed.
|
||
|
|
*
|
||
|
|
* Return: 0 on success, non-zero error code on failure.
|
||
|
|
*/
|
||
|
|
int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
|
||
|
|
{
|
||
|
|
struct drm_i915_private *i915 = slpc_to_i915(slpc);
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
GEM_BUG_ON(!slpc->vma);
|
||
|
|
|
||
|
|
slpc_shared_data_reset(slpc->vaddr);
|
||
|
|
|
||
|
|
ret = slpc_reset(slpc);
|
||
|
|
if (unlikely(ret < 0)) {
|
||
|
|
drm_err(&i915->drm, "SLPC Reset event returned (%pe)\n",
|
||
|
|
ERR_PTR(ret));
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = slpc_query_task_state(slpc);
|
||
|
|
if (unlikely(ret < 0))
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
intel_guc_pm_intrmsk_enable(&i915->gt);
|
||
|
|
|
||
|
|
slpc_get_rp_values(slpc);
|
||
|
|
|
||
|
|
/* Ignore efficient freq and set min to platform min */
|
||
|
|
ret = slpc_ignore_eff_freq(slpc, true);
|
||
|
|
if (unlikely(ret)) {
|
||
|
|
drm_err(&i915->drm, "Failed to set SLPC min to RPn (%pe)\n",
|
||
|
|
ERR_PTR(ret));
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Set SLPC max limit to RP0 */
|
||
|
|
ret = slpc_use_fused_rp0(slpc);
|
||
|
|
if (unlikely(ret)) {
|
||
|
|
drm_err(&i915->drm, "Failed to set SLPC max to RP0 (%pe)\n",
|
||
|
|
ERR_PTR(ret));
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Revert SLPC min/max to softlimits if necessary */
|
||
|
|
ret = slpc_set_softlimits(slpc);
|
||
|
|
if (unlikely(ret)) {
|
||
|
|
drm_err(&i915->drm, "Failed to set SLPC softlimits (%pe)\n",
|
||
|
|
ERR_PTR(ret));
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p)
|
||
|
|
{
|
||
|
|
struct drm_i915_private *i915 = slpc_to_i915(slpc);
|
||
|
|
struct slpc_shared_data *data = slpc->vaddr;
|
||
|
|
struct slpc_task_state_data *slpc_tasks;
|
||
|
|
intel_wakeref_t wakeref;
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
GEM_BUG_ON(!slpc->vma);
|
||
|
|
|
||
|
|
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
|
||
|
|
ret = slpc_query_task_state(slpc);
|
||
|
|
|
||
|
|
if (!ret) {
|
||
|
|
slpc_tasks = &data->task_state_data;
|
||
|
|
|
||
|
|
drm_printf(p, "\tSLPC state: %s\n", slpc_get_state_string(slpc));
|
||
|
|
drm_printf(p, "\tGTPERF task active: %s\n",
|
||
|
|
yesno(slpc_tasks->status & SLPC_GTPERF_TASK_ENABLED));
|
||
|
|
drm_printf(p, "\tMax freq: %u MHz\n",
|
||
|
|
slpc_decode_max_freq(slpc));
|
||
|
|
drm_printf(p, "\tMin freq: %u MHz\n",
|
||
|
|
slpc_decode_min_freq(slpc));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
|
||
|
|
{
|
||
|
|
if (!slpc->vma)
|
||
|
|
return;
|
||
|
|
|
||
|
|
i915_vma_unpin_and_release(&slpc->vma, I915_VMA_RELEASE_MAP);
|
||
|
|
}
|