439 lines
9.7 KiB
C
439 lines
9.7 KiB
C
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/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2017 Intel Corporation
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*/
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#include <linux/prime_numbers.h>
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#include "gt/intel_engine_pm.h"
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#include "gt/intel_gpu_commands.h"
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#include "gt/intel_gt.h"
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#include "gt/intel_gt_pm.h"
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#include "gt/intel_ring.h"
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#include "i915_selftest.h"
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#include "selftests/i915_random.h"
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struct context {
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struct drm_i915_gem_object *obj;
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struct intel_engine_cs *engine;
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};
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static int cpu_set(struct context *ctx, unsigned long offset, u32 v)
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{
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unsigned int needs_clflush;
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struct page *page;
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void *map;
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u32 *cpu;
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int err;
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i915_gem_object_lock(ctx->obj, NULL);
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err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush);
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if (err)
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goto out;
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page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT);
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map = kmap_atomic(page);
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cpu = map + offset_in_page(offset);
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if (needs_clflush & CLFLUSH_BEFORE)
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drm_clflush_virt_range(cpu, sizeof(*cpu));
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*cpu = v;
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if (needs_clflush & CLFLUSH_AFTER)
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drm_clflush_virt_range(cpu, sizeof(*cpu));
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kunmap_atomic(map);
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i915_gem_object_finish_access(ctx->obj);
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out:
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i915_gem_object_unlock(ctx->obj);
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return err;
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}
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static int cpu_get(struct context *ctx, unsigned long offset, u32 *v)
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{
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unsigned int needs_clflush;
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struct page *page;
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void *map;
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u32 *cpu;
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int err;
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i915_gem_object_lock(ctx->obj, NULL);
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err = i915_gem_object_prepare_read(ctx->obj, &needs_clflush);
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if (err)
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goto out;
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page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT);
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map = kmap_atomic(page);
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cpu = map + offset_in_page(offset);
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if (needs_clflush & CLFLUSH_BEFORE)
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drm_clflush_virt_range(cpu, sizeof(*cpu));
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*v = *cpu;
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kunmap_atomic(map);
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i915_gem_object_finish_access(ctx->obj);
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out:
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i915_gem_object_unlock(ctx->obj);
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return err;
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}
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static int gtt_set(struct context *ctx, unsigned long offset, u32 v)
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{
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struct i915_vma *vma;
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u32 __iomem *map;
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int err = 0;
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i915_gem_object_lock(ctx->obj, NULL);
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err = i915_gem_object_set_to_gtt_domain(ctx->obj, true);
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i915_gem_object_unlock(ctx->obj);
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if (err)
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return err;
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vma = i915_gem_object_ggtt_pin(ctx->obj, NULL, 0, 0, PIN_MAPPABLE);
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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intel_gt_pm_get(vma->vm->gt);
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map = i915_vma_pin_iomap(vma);
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i915_vma_unpin(vma);
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if (IS_ERR(map)) {
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err = PTR_ERR(map);
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goto out_rpm;
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}
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iowrite32(v, &map[offset / sizeof(*map)]);
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i915_vma_unpin_iomap(vma);
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out_rpm:
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intel_gt_pm_put(vma->vm->gt);
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return err;
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}
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static int gtt_get(struct context *ctx, unsigned long offset, u32 *v)
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{
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struct i915_vma *vma;
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u32 __iomem *map;
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int err = 0;
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i915_gem_object_lock(ctx->obj, NULL);
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err = i915_gem_object_set_to_gtt_domain(ctx->obj, false);
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i915_gem_object_unlock(ctx->obj);
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if (err)
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return err;
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vma = i915_gem_object_ggtt_pin(ctx->obj, NULL, 0, 0, PIN_MAPPABLE);
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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intel_gt_pm_get(vma->vm->gt);
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map = i915_vma_pin_iomap(vma);
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i915_vma_unpin(vma);
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if (IS_ERR(map)) {
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err = PTR_ERR(map);
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goto out_rpm;
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}
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*v = ioread32(&map[offset / sizeof(*map)]);
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i915_vma_unpin_iomap(vma);
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out_rpm:
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intel_gt_pm_put(vma->vm->gt);
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return err;
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}
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static int wc_set(struct context *ctx, unsigned long offset, u32 v)
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{
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u32 *map;
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int err;
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i915_gem_object_lock(ctx->obj, NULL);
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err = i915_gem_object_set_to_wc_domain(ctx->obj, true);
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i915_gem_object_unlock(ctx->obj);
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if (err)
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return err;
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map = i915_gem_object_pin_map_unlocked(ctx->obj, I915_MAP_WC);
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if (IS_ERR(map))
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return PTR_ERR(map);
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map[offset / sizeof(*map)] = v;
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__i915_gem_object_flush_map(ctx->obj, offset, sizeof(*map));
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i915_gem_object_unpin_map(ctx->obj);
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return 0;
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}
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static int wc_get(struct context *ctx, unsigned long offset, u32 *v)
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{
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u32 *map;
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int err;
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i915_gem_object_lock(ctx->obj, NULL);
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err = i915_gem_object_set_to_wc_domain(ctx->obj, false);
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i915_gem_object_unlock(ctx->obj);
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if (err)
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return err;
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map = i915_gem_object_pin_map_unlocked(ctx->obj, I915_MAP_WC);
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if (IS_ERR(map))
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return PTR_ERR(map);
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*v = map[offset / sizeof(*map)];
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i915_gem_object_unpin_map(ctx->obj);
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return 0;
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}
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static int gpu_set(struct context *ctx, unsigned long offset, u32 v)
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{
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struct i915_request *rq;
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struct i915_vma *vma;
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u32 *cs;
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int err;
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vma = i915_gem_object_ggtt_pin(ctx->obj, NULL, 0, 0, 0);
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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i915_gem_object_lock(ctx->obj, NULL);
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err = i915_gem_object_set_to_gtt_domain(ctx->obj, true);
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if (err)
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goto out_unlock;
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rq = intel_engine_create_kernel_request(ctx->engine);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto out_unpin;
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}
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cs = intel_ring_begin(rq, 4);
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if (IS_ERR(cs)) {
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err = PTR_ERR(cs);
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goto out_rq;
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}
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if (GRAPHICS_VER(ctx->engine->i915) >= 8) {
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*cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
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*cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset);
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*cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);
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*cs++ = v;
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} else if (GRAPHICS_VER(ctx->engine->i915) >= 4) {
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*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
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*cs++ = 0;
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*cs++ = i915_ggtt_offset(vma) + offset;
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*cs++ = v;
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} else {
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*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
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*cs++ = i915_ggtt_offset(vma) + offset;
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*cs++ = v;
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*cs++ = MI_NOOP;
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}
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intel_ring_advance(rq, cs);
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err = i915_request_await_object(rq, vma->obj, true);
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if (err == 0)
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err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
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out_rq:
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i915_request_add(rq);
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out_unpin:
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i915_vma_unpin(vma);
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out_unlock:
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i915_gem_object_unlock(ctx->obj);
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return err;
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}
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static bool always_valid(struct context *ctx)
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{
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return true;
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}
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static bool needs_fence_registers(struct context *ctx)
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{
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struct intel_gt *gt = ctx->engine->gt;
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if (intel_gt_is_wedged(gt))
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return false;
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return gt->ggtt->num_fences;
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}
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static bool needs_mi_store_dword(struct context *ctx)
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{
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if (intel_gt_is_wedged(ctx->engine->gt))
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return false;
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return intel_engine_can_store_dword(ctx->engine);
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}
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static const struct igt_coherency_mode {
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const char *name;
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int (*set)(struct context *ctx, unsigned long offset, u32 v);
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int (*get)(struct context *ctx, unsigned long offset, u32 *v);
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bool (*valid)(struct context *ctx);
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} igt_coherency_mode[] = {
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{ "cpu", cpu_set, cpu_get, always_valid },
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{ "gtt", gtt_set, gtt_get, needs_fence_registers },
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{ "wc", wc_set, wc_get, always_valid },
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{ "gpu", gpu_set, NULL, needs_mi_store_dword },
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{ },
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};
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static struct intel_engine_cs *
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random_engine(struct drm_i915_private *i915, struct rnd_state *prng)
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{
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struct intel_engine_cs *engine;
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unsigned int count;
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count = 0;
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for_each_uabi_engine(engine, i915)
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count++;
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count = i915_prandom_u32_max_state(count, prng);
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for_each_uabi_engine(engine, i915)
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if (count-- == 0)
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return engine;
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return NULL;
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}
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static int igt_gem_coherency(void *arg)
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{
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const unsigned int ncachelines = PAGE_SIZE/64;
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struct drm_i915_private *i915 = arg;
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const struct igt_coherency_mode *read, *write, *over;
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unsigned long count, n;
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u32 *offsets, *values;
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I915_RND_STATE(prng);
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struct context ctx;
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int err = 0;
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/*
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* We repeatedly write, overwrite and read from a sequence of
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* cachelines in order to try and detect incoherency (unflushed writes
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* from either the CPU or GPU). Each setter/getter uses our cache
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* domain API which should prevent incoherency.
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*/
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offsets = kmalloc_array(ncachelines, 2*sizeof(u32), GFP_KERNEL);
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if (!offsets)
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return -ENOMEM;
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for (count = 0; count < ncachelines; count++)
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offsets[count] = count * 64 + 4 * (count % 16);
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values = offsets + ncachelines;
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ctx.engine = random_engine(i915, &prng);
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if (!ctx.engine) {
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err = -ENODEV;
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goto out_free;
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}
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pr_info("%s: using %s\n", __func__, ctx.engine->name);
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intel_engine_pm_get(ctx.engine);
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for (over = igt_coherency_mode; over->name; over++) {
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if (!over->set)
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continue;
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if (!over->valid(&ctx))
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continue;
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for (write = igt_coherency_mode; write->name; write++) {
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if (!write->set)
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continue;
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if (!write->valid(&ctx))
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continue;
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for (read = igt_coherency_mode; read->name; read++) {
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if (!read->get)
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continue;
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if (!read->valid(&ctx))
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continue;
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for_each_prime_number_from(count, 1, ncachelines) {
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ctx.obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
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if (IS_ERR(ctx.obj)) {
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err = PTR_ERR(ctx.obj);
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goto out_pm;
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}
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i915_random_reorder(offsets, ncachelines, &prng);
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for (n = 0; n < count; n++)
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values[n] = prandom_u32_state(&prng);
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for (n = 0; n < count; n++) {
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err = over->set(&ctx, offsets[n], ~values[n]);
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if (err) {
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|
|
pr_err("Failed to set stale value[%ld/%ld] in object using %s, err=%d\n",
|
||
|
|
n, count, over->name, err);
|
||
|
|
goto put_object;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
for (n = 0; n < count; n++) {
|
||
|
|
err = write->set(&ctx, offsets[n], values[n]);
|
||
|
|
if (err) {
|
||
|
|
pr_err("Failed to set value[%ld/%ld] in object using %s, err=%d\n",
|
||
|
|
n, count, write->name, err);
|
||
|
|
goto put_object;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
for (n = 0; n < count; n++) {
|
||
|
|
u32 found;
|
||
|
|
|
||
|
|
err = read->get(&ctx, offsets[n], &found);
|
||
|
|
if (err) {
|
||
|
|
pr_err("Failed to get value[%ld/%ld] in object using %s, err=%d\n",
|
||
|
|
n, count, read->name, err);
|
||
|
|
goto put_object;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (found != values[n]) {
|
||
|
|
pr_err("Value[%ld/%ld] mismatch, (overwrite with %s) wrote [%s] %x read [%s] %x (inverse %x), at offset %x\n",
|
||
|
|
n, count, over->name,
|
||
|
|
write->name, values[n],
|
||
|
|
read->name, found,
|
||
|
|
~values[n], offsets[n]);
|
||
|
|
err = -EINVAL;
|
||
|
|
goto put_object;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
i915_gem_object_put(ctx.obj);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
out_pm:
|
||
|
|
intel_engine_pm_put(ctx.engine);
|
||
|
|
out_free:
|
||
|
|
kfree(offsets);
|
||
|
|
return err;
|
||
|
|
|
||
|
|
put_object:
|
||
|
|
i915_gem_object_put(ctx.obj);
|
||
|
|
goto out_pm;
|
||
|
|
}
|
||
|
|
|
||
|
|
int i915_gem_coherency_live_selftests(struct drm_i915_private *i915)
|
||
|
|
{
|
||
|
|
static const struct i915_subtest tests[] = {
|
||
|
|
SUBTEST(igt_gem_coherency),
|
||
|
|
};
|
||
|
|
|
||
|
|
return i915_subtests(tests, i915);
|
||
|
|
}
|