403 lines
11 KiB
C
403 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Amarula Solutions(India)
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <drm/drm_of.h>
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#include <drm/drm_print.h>
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#include <drm/drm_mipi_dsi.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/regulator/consumer.h>
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#define VENDOR_ID 0x00
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#define DEVICE_ID_H 0x01
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#define DEVICE_ID_L 0x02
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#define VERSION_ID 0x03
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#define FIRMWARE_VERSION 0x08
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#define CONFIG_FINISH 0x09
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#define PD_CTRL(n) (0x0a + ((n) & 0x3)) /* 0..3 */
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#define RST_CTRL(n) (0x0e + ((n) & 0x1)) /* 0..1 */
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#define SYS_CTRL(n) (0x10 + ((n) & 0x7)) /* 0..4 */
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#define RGB_DRV(n) (0x18 + ((n) & 0x3)) /* 0..3 */
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#define RGB_DLY(n) (0x1c + ((n) & 0x1)) /* 0..1 */
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#define RGB_TEST_CTRL 0x1e
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#define ATE_PLL_EN 0x1f
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#define HACTIVE_LI 0x20
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#define VACTIVE_LI 0x21
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#define VACTIVE_HACTIVE_HI 0x22
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#define HFP_LI 0x23
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#define HSYNC_LI 0x24
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#define HBP_LI 0x25
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#define HFP_HSW_HBP_HI 0x26
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#define HFP_HSW_HBP_HI_HFP(n) (((n) & 0x300) >> 4)
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#define HFP_HSW_HBP_HI_HS(n) (((n) & 0x300) >> 6)
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#define HFP_HSW_HBP_HI_HBP(n) (((n) & 0x300) >> 8)
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#define VFP 0x27
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#define VSYNC 0x28
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#define VBP 0x29
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#define BIST_POL 0x2a
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#define BIST_POL_BIST_MODE(n) (((n) & 0xf) << 4)
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#define BIST_POL_BIST_GEN BIT(3)
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#define BIST_POL_HSYNC_POL BIT(2)
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#define BIST_POL_VSYNC_POL BIT(1)
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#define BIST_POL_DE_POL BIT(0)
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#define BIST_RED 0x2b
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#define BIST_GREEN 0x2c
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#define BIST_BLUE 0x2d
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#define BIST_CHESS_X 0x2e
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#define BIST_CHESS_Y 0x2f
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#define BIST_CHESS_XY_H 0x30
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#define BIST_FRAME_TIME_L 0x31
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#define BIST_FRAME_TIME_H 0x32
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#define FIFO_MAX_ADDR_LOW 0x33
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#define SYNC_EVENT_DLY 0x34
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#define HSW_MIN 0x35
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#define HFP_MIN 0x36
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#define LOGIC_RST_NUM 0x37
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#define OSC_CTRL(n) (0x48 + ((n) & 0x7)) /* 0..5 */
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#define BG_CTRL 0x4e
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#define LDO_PLL 0x4f
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#define PLL_CTRL(n) (0x50 + ((n) & 0xf)) /* 0..15 */
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#define PLL_CTRL_6_EXTERNAL 0x90
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#define PLL_CTRL_6_MIPI_CLK 0x92
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#define PLL_CTRL_6_INTERNAL 0x93
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#define PLL_REM(n) (0x60 + ((n) & 0x3)) /* 0..2 */
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#define PLL_DIV(n) (0x63 + ((n) & 0x3)) /* 0..2 */
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#define PLL_FRAC(n) (0x66 + ((n) & 0x3)) /* 0..2 */
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#define PLL_INT(n) (0x69 + ((n) & 0x1)) /* 0..1 */
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#define PLL_REF_DIV 0x6b
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#define PLL_REF_DIV_P(n) ((n) & 0xf)
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#define PLL_REF_DIV_Pe BIT(4)
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#define PLL_REF_DIV_S(n) (((n) & 0x7) << 5)
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#define PLL_SSC_P(n) (0x6c + ((n) & 0x3)) /* 0..2 */
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#define PLL_SSC_STEP(n) (0x6f + ((n) & 0x3)) /* 0..2 */
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#define PLL_SSC_OFFSET(n) (0x72 + ((n) & 0x3)) /* 0..3 */
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#define GPIO_OEN 0x79
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#define MIPI_CFG_PW 0x7a
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#define MIPI_CFG_PW_CONFIG_DSI 0xc1
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#define MIPI_CFG_PW_CONFIG_I2C 0x3e
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#define GPIO_SEL(n) (0x7b + ((n) & 0x1)) /* 0..1 */
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#define IRQ_SEL 0x7d
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#define DBG_SEL 0x7e
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#define DBG_SIGNAL 0x7f
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#define MIPI_ERR_VECTOR_L 0x80
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#define MIPI_ERR_VECTOR_H 0x81
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#define MIPI_ERR_VECTOR_EN_L 0x82
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#define MIPI_ERR_VECTOR_EN_H 0x83
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#define MIPI_MAX_SIZE_L 0x84
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#define MIPI_MAX_SIZE_H 0x85
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#define DSI_CTRL 0x86
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#define DSI_CTRL_UNKNOWN 0x28
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#define DSI_CTRL_DSI_LANES(n) ((n) & 0x3)
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#define MIPI_PN_SWAP 0x87
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#define MIPI_PN_SWAP_CLK BIT(4)
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#define MIPI_PN_SWAP_D(n) BIT((n) & 0x3)
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#define MIPI_SOT_SYNC_BIT_(n) (0x88 + ((n) & 0x1)) /* 0..1 */
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#define MIPI_ULPS_CTRL 0x8a
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#define MIPI_CLK_CHK_VAR 0x8e
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#define MIPI_CLK_CHK_INI 0x8f
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#define MIPI_T_TERM_EN 0x90
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#define MIPI_T_HS_SETTLE 0x91
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#define MIPI_T_TA_SURE_PRE 0x92
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#define MIPI_T_LPX_SET 0x94
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#define MIPI_T_CLK_MISS 0x95
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#define MIPI_INIT_TIME_L 0x96
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#define MIPI_INIT_TIME_H 0x97
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#define MIPI_T_CLK_TERM_EN 0x99
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#define MIPI_T_CLK_SETTLE 0x9a
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#define MIPI_TO_HS_RX_L 0x9e
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#define MIPI_TO_HS_RX_H 0x9f
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#define MIPI_PHY_(n) (0xa0 + ((n) & 0x7)) /* 0..5 */
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#define MIPI_PD_RX 0xb0
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#define MIPI_PD_TERM 0xb1
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#define MIPI_PD_HSRX 0xb2
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#define MIPI_PD_LPTX 0xb3
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#define MIPI_PD_LPRX 0xb4
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#define MIPI_PD_CK_LANE 0xb5
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#define MIPI_FORCE_0 0xb6
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#define MIPI_RST_CTRL 0xb7
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#define MIPI_RST_NUM 0xb8
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#define MIPI_DBG_SET_(n) (0xc0 + ((n) & 0xf)) /* 0..9 */
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#define MIPI_DBG_SEL 0xe0
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#define MIPI_DBG_DATA 0xe1
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#define MIPI_ATE_TEST_SEL 0xe2
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#define MIPI_ATE_STATUS_(n) (0xe3 + ((n) & 0x1)) /* 0..1 */
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#define MIPI_ATE_STATUS_1 0xe4
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#define ICN6211_MAX_REGISTER MIPI_ATE_STATUS(1)
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struct chipone {
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struct device *dev;
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struct drm_bridge bridge;
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struct drm_bridge *panel_bridge;
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struct gpio_desc *enable_gpio;
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struct regulator *vdd1;
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struct regulator *vdd2;
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struct regulator *vdd3;
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};
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static inline struct chipone *bridge_to_chipone(struct drm_bridge *bridge)
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{
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return container_of(bridge, struct chipone, bridge);
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}
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static struct drm_display_mode *bridge_to_mode(struct drm_bridge *bridge)
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{
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return &bridge->encoder->crtc->state->adjusted_mode;
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}
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static inline int chipone_dsi_write(struct chipone *icn, const void *seq,
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size_t len)
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{
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(icn->dev);
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return mipi_dsi_generic_write(dsi, seq, len);
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}
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#define ICN6211_DSI(icn, seq...) \
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{ \
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const u8 d[] = { seq }; \
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chipone_dsi_write(icn, d, ARRAY_SIZE(d)); \
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}
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static void chipone_enable(struct drm_bridge *bridge)
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{
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struct chipone *icn = bridge_to_chipone(bridge);
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struct drm_display_mode *mode = bridge_to_mode(bridge);
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u16 hfp, hbp, hsync;
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ICN6211_DSI(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_DSI);
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ICN6211_DSI(icn, HACTIVE_LI, mode->hdisplay & 0xff);
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ICN6211_DSI(icn, VACTIVE_LI, mode->vdisplay & 0xff);
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/*
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* lsb nibble: 2nd nibble of hdisplay
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* msb nibble: 2nd nibble of vdisplay
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*/
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ICN6211_DSI(icn, VACTIVE_HACTIVE_HI,
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((mode->hdisplay >> 8) & 0xf) |
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(((mode->vdisplay >> 8) & 0xf) << 4));
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hfp = mode->hsync_start - mode->hdisplay;
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hsync = mode->hsync_end - mode->hsync_start;
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hbp = mode->htotal - mode->hsync_end;
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ICN6211_DSI(icn, HFP_LI, hfp & 0xff);
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ICN6211_DSI(icn, HSYNC_LI, hsync & 0xff);
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ICN6211_DSI(icn, HBP_LI, hbp & 0xff);
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/* Top two bits of Horizontal Front porch/Sync/Back porch */
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ICN6211_DSI(icn, HFP_HSW_HBP_HI,
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HFP_HSW_HBP_HI_HFP(hfp) |
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HFP_HSW_HBP_HI_HS(hsync) |
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HFP_HSW_HBP_HI_HBP(hbp));
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ICN6211_DSI(icn, VFP, mode->vsync_start - mode->vdisplay);
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ICN6211_DSI(icn, VSYNC, mode->vsync_end - mode->vsync_start);
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ICN6211_DSI(icn, VBP, mode->vtotal - mode->vsync_end);
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/* dsi specific sequence */
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ICN6211_DSI(icn, SYNC_EVENT_DLY, 0x80);
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ICN6211_DSI(icn, HFP_MIN, hfp & 0xff);
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ICN6211_DSI(icn, MIPI_PD_CK_LANE, 0xa0);
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ICN6211_DSI(icn, PLL_CTRL(12), 0xff);
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ICN6211_DSI(icn, BIST_POL, BIST_POL_DE_POL);
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ICN6211_DSI(icn, PLL_CTRL(6), PLL_CTRL_6_MIPI_CLK);
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ICN6211_DSI(icn, PLL_REF_DIV, 0x71);
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ICN6211_DSI(icn, PLL_INT(0), 0x2b);
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ICN6211_DSI(icn, SYS_CTRL(0), 0x40);
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ICN6211_DSI(icn, SYS_CTRL(1), 0x98);
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/* icn6211 specific sequence */
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ICN6211_DSI(icn, MIPI_FORCE_0, 0x20);
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ICN6211_DSI(icn, PLL_CTRL(1), 0x20);
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ICN6211_DSI(icn, CONFIG_FINISH, 0x10);
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usleep_range(10000, 11000);
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}
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static void chipone_pre_enable(struct drm_bridge *bridge)
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{
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struct chipone *icn = bridge_to_chipone(bridge);
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int ret;
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if (icn->vdd1) {
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ret = regulator_enable(icn->vdd1);
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if (ret)
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DRM_DEV_ERROR(icn->dev,
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"failed to enable VDD1 regulator: %d\n", ret);
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}
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if (icn->vdd2) {
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ret = regulator_enable(icn->vdd2);
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if (ret)
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DRM_DEV_ERROR(icn->dev,
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"failed to enable VDD2 regulator: %d\n", ret);
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}
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if (icn->vdd3) {
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ret = regulator_enable(icn->vdd3);
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if (ret)
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DRM_DEV_ERROR(icn->dev,
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"failed to enable VDD3 regulator: %d\n", ret);
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}
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gpiod_set_value(icn->enable_gpio, 1);
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usleep_range(10000, 11000);
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}
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static void chipone_post_disable(struct drm_bridge *bridge)
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{
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struct chipone *icn = bridge_to_chipone(bridge);
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if (icn->vdd1)
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regulator_disable(icn->vdd1);
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if (icn->vdd2)
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regulator_disable(icn->vdd2);
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if (icn->vdd3)
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regulator_disable(icn->vdd3);
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gpiod_set_value(icn->enable_gpio, 0);
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}
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static int chipone_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags)
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{
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struct chipone *icn = bridge_to_chipone(bridge);
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return drm_bridge_attach(bridge->encoder, icn->panel_bridge, bridge, flags);
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}
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static const struct drm_bridge_funcs chipone_bridge_funcs = {
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.attach = chipone_attach,
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.post_disable = chipone_post_disable,
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.pre_enable = chipone_pre_enable,
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.enable = chipone_enable,
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};
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static int chipone_parse_dt(struct chipone *icn)
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{
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struct device *dev = icn->dev;
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struct drm_panel *panel;
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int ret;
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icn->vdd1 = devm_regulator_get_optional(dev, "vdd1");
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if (IS_ERR(icn->vdd1)) {
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ret = PTR_ERR(icn->vdd1);
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if (ret == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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icn->vdd1 = NULL;
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DRM_DEV_DEBUG(dev, "failed to get VDD1 regulator: %d\n", ret);
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}
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icn->vdd2 = devm_regulator_get_optional(dev, "vdd2");
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if (IS_ERR(icn->vdd2)) {
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ret = PTR_ERR(icn->vdd2);
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if (ret == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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icn->vdd2 = NULL;
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DRM_DEV_DEBUG(dev, "failed to get VDD2 regulator: %d\n", ret);
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}
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icn->vdd3 = devm_regulator_get_optional(dev, "vdd3");
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if (IS_ERR(icn->vdd3)) {
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ret = PTR_ERR(icn->vdd3);
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|
if (ret == -EPROBE_DEFER)
|
||
|
|
return -EPROBE_DEFER;
|
||
|
|
icn->vdd3 = NULL;
|
||
|
|
DRM_DEV_DEBUG(dev, "failed to get VDD3 regulator: %d\n", ret);
|
||
|
|
}
|
||
|
|
|
||
|
|
icn->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
|
||
|
|
if (IS_ERR(icn->enable_gpio)) {
|
||
|
|
DRM_DEV_ERROR(dev, "failed to get enable GPIO\n");
|
||
|
|
return PTR_ERR(icn->enable_gpio);
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
icn->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
|
||
|
|
if (IS_ERR(icn->panel_bridge))
|
||
|
|
return PTR_ERR(icn->panel_bridge);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int chipone_probe(struct mipi_dsi_device *dsi)
|
||
|
|
{
|
||
|
|
struct device *dev = &dsi->dev;
|
||
|
|
struct chipone *icn;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
icn = devm_kzalloc(dev, sizeof(struct chipone), GFP_KERNEL);
|
||
|
|
if (!icn)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
mipi_dsi_set_drvdata(dsi, icn);
|
||
|
|
icn->dev = dev;
|
||
|
|
|
||
|
|
ret = chipone_parse_dt(icn);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
icn->bridge.funcs = &chipone_bridge_funcs;
|
||
|
|
icn->bridge.type = DRM_MODE_CONNECTOR_DPI;
|
||
|
|
icn->bridge.of_node = dev->of_node;
|
||
|
|
|
||
|
|
drm_bridge_add(&icn->bridge);
|
||
|
|
|
||
|
|
dsi->lanes = 4;
|
||
|
|
dsi->format = MIPI_DSI_FMT_RGB888;
|
||
|
|
dsi->mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
|
||
|
|
|
||
|
|
ret = mipi_dsi_attach(dsi);
|
||
|
|
if (ret < 0) {
|
||
|
|
drm_bridge_remove(&icn->bridge);
|
||
|
|
dev_err(dev, "failed to attach dsi\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int chipone_remove(struct mipi_dsi_device *dsi)
|
||
|
|
{
|
||
|
|
struct chipone *icn = mipi_dsi_get_drvdata(dsi);
|
||
|
|
|
||
|
|
mipi_dsi_detach(dsi);
|
||
|
|
drm_bridge_remove(&icn->bridge);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id chipone_of_match[] = {
|
||
|
|
{ .compatible = "chipone,icn6211", },
|
||
|
|
{ /* sentinel */ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, chipone_of_match);
|
||
|
|
|
||
|
|
static struct mipi_dsi_driver chipone_driver = {
|
||
|
|
.probe = chipone_probe,
|
||
|
|
.remove = chipone_remove,
|
||
|
|
.driver = {
|
||
|
|
.name = "chipone-icn6211",
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
.of_match_table = chipone_of_match,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
module_mipi_dsi_driver(chipone_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
|
||
|
|
MODULE_DESCRIPTION("Chipone ICN6211 MIPI-DSI to RGB Converter Bridge");
|
||
|
|
MODULE_LICENSE("GPL");
|