219 lines
5.0 KiB
C
219 lines
5.0 KiB
C
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/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#include "amdgpu.h"
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#include "cikd.h"
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#include "kv_dpm.h"
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#include "smu/smu_7_0_0_d.h"
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#include "smu/smu_7_0_0_sh_mask.h"
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int amdgpu_kv_notify_message_to_smu(struct amdgpu_device *adev, u32 id)
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{
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u32 i;
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u32 tmp = 0;
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WREG32(mmSMC_MESSAGE_0, id & SMC_MESSAGE_0__SMC_MSG_MASK);
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for (i = 0; i < adev->usec_timeout; i++) {
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if ((RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK) != 0)
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break;
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udelay(1);
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}
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tmp = RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK;
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if (tmp != 1) {
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if (tmp == 0xFF)
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return -EINVAL;
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else if (tmp == 0xFE)
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return -EINVAL;
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}
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return 0;
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}
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int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask)
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{
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int ret;
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ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SCLKDPM_GetEnabledMask);
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if (ret == 0)
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*enable_mask = RREG32_SMC(ixSMC_SYSCON_MSG_ARG_0);
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return ret;
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}
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int amdgpu_kv_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
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PPSMC_Msg msg, u32 parameter)
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{
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WREG32(mmSMC_MSG_ARG_0, parameter);
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return amdgpu_kv_notify_message_to_smu(adev, msg);
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}
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static int kv_set_smc_sram_address(struct amdgpu_device *adev,
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u32 smc_address, u32 limit)
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{
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if (smc_address & 3)
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return -EINVAL;
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if ((smc_address + 3) > limit)
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return -EINVAL;
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WREG32(mmSMC_IND_INDEX_0, smc_address);
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WREG32_P(mmSMC_IND_ACCESS_CNTL, 0,
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~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);
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return 0;
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}
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int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
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u32 *value, u32 limit)
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{
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int ret;
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ret = kv_set_smc_sram_address(adev, smc_address, limit);
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if (ret)
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return ret;
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*value = RREG32(mmSMC_IND_DATA_0);
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return 0;
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}
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int amdgpu_kv_smc_dpm_enable(struct amdgpu_device *adev, bool enable)
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{
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if (enable)
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return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DPM_Enable);
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else
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return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DPM_Disable);
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}
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int amdgpu_kv_smc_bapm_enable(struct amdgpu_device *adev, bool enable)
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{
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if (enable)
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return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableBAPM);
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else
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return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableBAPM);
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}
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int amdgpu_kv_copy_bytes_to_smc(struct amdgpu_device *adev,
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u32 smc_start_address,
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const u8 *src, u32 byte_count, u32 limit)
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{
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int ret;
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u32 data, original_data, addr, extra_shift, t_byte, count, mask;
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if ((smc_start_address + byte_count) > limit)
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return -EINVAL;
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addr = smc_start_address;
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t_byte = addr & 3;
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/* RMW for the initial bytes */
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if (t_byte != 0) {
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addr -= t_byte;
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ret = kv_set_smc_sram_address(adev, addr, limit);
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if (ret)
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return ret;
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original_data = RREG32(mmSMC_IND_DATA_0);
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data = 0;
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mask = 0;
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count = 4;
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while (count > 0) {
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if (t_byte > 0) {
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mask = (mask << 8) | 0xff;
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t_byte--;
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} else if (byte_count > 0) {
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data = (data << 8) + *src++;
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byte_count--;
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mask <<= 8;
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} else {
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data <<= 8;
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mask = (mask << 8) | 0xff;
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}
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count--;
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}
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data |= original_data & mask;
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ret = kv_set_smc_sram_address(adev, addr, limit);
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if (ret)
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return ret;
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WREG32(mmSMC_IND_DATA_0, data);
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addr += 4;
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}
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while (byte_count >= 4) {
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/* SMC address space is BE */
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data = (src[0] << 24) + (src[1] << 16) + (src[2] << 8) + src[3];
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ret = kv_set_smc_sram_address(adev, addr, limit);
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if (ret)
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return ret;
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WREG32(mmSMC_IND_DATA_0, data);
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src += 4;
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byte_count -= 4;
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addr += 4;
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}
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/* RMW for the final bytes */
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if (byte_count > 0) {
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data = 0;
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ret = kv_set_smc_sram_address(adev, addr, limit);
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if (ret)
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return ret;
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original_data = RREG32(mmSMC_IND_DATA_0);
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extra_shift = 8 * (4 - byte_count);
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while (byte_count > 0) {
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/* SMC address space is BE */
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data = (data << 8) + *src++;
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byte_count--;
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}
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data <<= extra_shift;
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data |= (original_data & ~((~0UL) << extra_shift));
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ret = kv_set_smc_sram_address(adev, addr, limit);
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if (ret)
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return ret;
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WREG32(mmSMC_IND_DATA_0, data);
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}
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return 0;
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}
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