82 lines
3.1 KiB
C
82 lines
3.1 KiB
C
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DCN30_DCCG_H__
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#define __DCN30_DCCG_H__
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#include "dcn20/dcn20_dccg.h"
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#define DCCG_REG_LIST_DCN3AG() \
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DCCG_COMMON_REG_LIST_DCN_BASE(),\
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SR(PHYASYMCLK_CLOCK_CNTL),\
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SR(PHYBSYMCLK_CLOCK_CNTL),\
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SR(PHYCSYMCLK_CLOCK_CNTL)
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#define DCCG_REG_LIST_DCN30() \
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DCCG_REG_LIST_DCN2(),\
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DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
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DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
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DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
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DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\
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SR(PHYASYMCLK_CLOCK_CNTL),\
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SR(PHYBSYMCLK_CLOCK_CNTL),\
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SR(PHYCSYMCLK_CLOCK_CNTL)
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#define DCCG_MASK_SH_LIST_DCN3AG(mask_sh) \
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DCCG_MASK_SH_LIST_DCN2_1(mask_sh),\
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DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
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DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
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DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
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DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
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DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
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DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
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DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
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DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh)
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#define DCCG_MASK_SH_LIST_DCN3(mask_sh) \
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DCCG_MASK_SH_LIST_DCN2(mask_sh),\
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DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
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DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
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DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
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DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
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DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
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DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
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struct dccg *dccg3_create(
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struct dc_context *ctx,
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const struct dccg_registers *regs,
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const struct dccg_shift *dccg_shift,
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const struct dccg_mask *dccg_mask);
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struct dccg *dccg30_create(
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struct dc_context *ctx,
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const struct dccg_registers *regs,
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const struct dccg_shift *dccg_shift,
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const struct dccg_mask *dccg_mask);
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#endif //__DCN30_DCCG_H__
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