322 lines
12 KiB
C
322 lines
12 KiB
C
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/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_AUX_ENGINE_DCE110_H__
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#define __DAL_AUX_ENGINE_DCE110_H__
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#include "i2caux_interface.h"
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#include "inc/hw/aux_engine.h"
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enum aux_return_code_type;
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#define AUX_COMMON_REG_LIST0(id)\
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SRI(AUX_CONTROL, DP_AUX, id), \
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SRI(AUX_ARB_CONTROL, DP_AUX, id), \
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SRI(AUX_SW_DATA, DP_AUX, id), \
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SRI(AUX_SW_CONTROL, DP_AUX, id), \
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SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
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SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id), \
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SRI(AUX_SW_STATUS, DP_AUX, id)
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#define AUX_COMMON_REG_LIST(id)\
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SRI(AUX_CONTROL, DP_AUX, id), \
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SRI(AUX_ARB_CONTROL, DP_AUX, id), \
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SRI(AUX_SW_DATA, DP_AUX, id), \
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SRI(AUX_SW_CONTROL, DP_AUX, id), \
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SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
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SRI(AUX_SW_STATUS, DP_AUX, id), \
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SR(AUXN_IMPCAL), \
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SR(AUXP_IMPCAL)
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struct dce110_aux_registers {
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uint32_t AUX_CONTROL;
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uint32_t AUX_ARB_CONTROL;
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uint32_t AUX_SW_DATA;
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uint32_t AUX_SW_CONTROL;
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uint32_t AUX_INTERRUPT_CONTROL;
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uint32_t AUX_DPHY_RX_CONTROL1;
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uint32_t AUX_SW_STATUS;
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uint32_t AUXN_IMPCAL;
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uint32_t AUXP_IMPCAL;
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uint32_t AUX_RESET_MASK;
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};
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#define DCE_AUX_REG_FIELD_LIST(type)\
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type AUX_EN;\
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type AUX_RESET;\
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type AUX_RESET_DONE;\
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type AUX_REG_RW_CNTL_STATUS;\
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type AUX_SW_USE_AUX_REG_REQ;\
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type AUX_SW_DONE_USING_AUX_REG;\
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type AUX_SW_AUTOINCREMENT_DISABLE;\
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type AUX_SW_DATA_RW;\
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type AUX_SW_INDEX;\
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type AUX_SW_GO;\
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type AUX_SW_DATA;\
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type AUX_SW_REPLY_BYTE_COUNT;\
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type AUX_SW_DONE;\
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type AUX_SW_DONE_ACK;\
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type AUXN_IMPCAL_ENABLE;\
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type AUXP_IMPCAL_ENABLE;\
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type AUXN_IMPCAL_OVERRIDE_ENABLE;\
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type AUXP_IMPCAL_OVERRIDE_ENABLE;\
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type AUX_RX_TIMEOUT_LEN;\
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type AUX_RX_TIMEOUT_LEN_MUL;\
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type AUXN_CALOUT_ERROR_AK;\
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type AUXP_CALOUT_ERROR_AK;\
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type AUX_SW_START_DELAY;\
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type AUX_SW_WR_BYTES
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#define DCE10_AUX_MASK_SH_LIST(mask_sh)\
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AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
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AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
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AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
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AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
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AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
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AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
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AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
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AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
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AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
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AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
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AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
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AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
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AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
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AUX_SF(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
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AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
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AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
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AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
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AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
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AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
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AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
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#define DCE_AUX_MASK_SH_LIST(mask_sh)\
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AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
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AUX_SF(AUX_CONTROL, AUX_RESET, mask_sh),\
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AUX_SF(AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
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AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
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AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
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AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
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AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
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AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
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AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
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AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
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AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
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AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
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AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
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AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
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AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
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AUX_SF(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
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AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
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AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
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AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
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AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
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AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
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AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
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#define DCE12_AUX_MASK_SH_LIST(mask_sh)\
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AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\
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AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\
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AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
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AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
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AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
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AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
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AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
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AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
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AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
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AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
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AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
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AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
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AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
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/* DCN10 MASK */
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#define DCN10_AUX_MASK_SH_LIST(mask_sh)\
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AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\
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AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\
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AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
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AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
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AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
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AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
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AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
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AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
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AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
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AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
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AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
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AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
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AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
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/* for all other DCN */
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#define DCN_AUX_MASK_SH_LIST(mask_sh)\
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AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\
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AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\
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AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
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AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
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AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
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AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
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AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
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AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
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AUX_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\
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AUX_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh)
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#define AUX_SF(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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enum { /* This is the timeout as defined in DP 1.2a,
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* 2.3.4 "Detailed uPacket TX AUX CH State Description".
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*/
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AUX_TIMEOUT_PERIOD = 400,
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/* Ideally, the SW timeout should be just above 550usec
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* which is programmed in HW.
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* But the SW timeout of 600usec is not reliable,
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* because on some systems, delay_in_microseconds()
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* returns faster than it should.
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* EPR #379763: by trial-and-error on different systems,
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* 700usec is the minimum reliable SW timeout for polling
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* the AUX_SW_STATUS.AUX_SW_DONE bit.
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* This timeout expires *only* when there is
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* AUX Error or AUX Timeout conditions - not during normal operation.
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* During normal operation, AUX_SW_STATUS.AUX_SW_DONE bit is set
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* at most within ~240usec. That means,
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* increasing this timeout will not affect normal operation,
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* and we'll timeout after
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* SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 2400usec.
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* This timeout is especially important for
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* converters, resume from S3, and CTS.
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*/
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SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 6
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};
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struct dce_aux {
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uint32_t inst;
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struct ddc *ddc;
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struct dc_context *ctx;
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/* following values are expressed in milliseconds */
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uint32_t delay;
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uint32_t max_defer_write_retry;
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bool acquire_reset;
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struct dce_aux_funcs *funcs;
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};
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struct dce110_aux_registers_mask {
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DCE_AUX_REG_FIELD_LIST(uint32_t);
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};
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struct dce110_aux_registers_shift {
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DCE_AUX_REG_FIELD_LIST(uint8_t);
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};
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struct aux_engine_dce110 {
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struct dce_aux base;
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const struct dce110_aux_registers *regs;
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const struct dce110_aux_registers_mask *mask;
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const struct dce110_aux_registers_shift *shift;
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|
|
struct {
|
||
|
|
uint32_t aux_control;
|
||
|
|
uint32_t aux_arb_control;
|
||
|
|
uint32_t aux_sw_data;
|
||
|
|
uint32_t aux_sw_control;
|
||
|
|
uint32_t aux_interrupt_control;
|
||
|
|
uint32_t aux_dphy_rx_control1;
|
||
|
|
uint32_t aux_dphy_rx_control0;
|
||
|
|
uint32_t aux_sw_status;
|
||
|
|
} addr;
|
||
|
|
uint32_t polling_timeout_period;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct aux_engine_dce110_init_data {
|
||
|
|
uint32_t engine_id;
|
||
|
|
uint32_t timeout_period;
|
||
|
|
struct dc_context *ctx;
|
||
|
|
const struct dce110_aux_registers *regs;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110,
|
||
|
|
struct dc_context *ctx,
|
||
|
|
uint32_t inst,
|
||
|
|
uint32_t timeout_period,
|
||
|
|
const struct dce110_aux_registers *regs,
|
||
|
|
|
||
|
|
const struct dce110_aux_registers_mask *mask,
|
||
|
|
const struct dce110_aux_registers_shift *shift,
|
||
|
|
bool is_ext_aux_timeout_configurable);
|
||
|
|
|
||
|
|
void dce110_engine_destroy(struct dce_aux **engine);
|
||
|
|
|
||
|
|
bool dce110_aux_engine_acquire(
|
||
|
|
struct dce_aux *aux_engine,
|
||
|
|
struct ddc *ddc);
|
||
|
|
|
||
|
|
int dce_aux_transfer_raw(struct ddc_service *ddc,
|
||
|
|
struct aux_payload *cmd,
|
||
|
|
enum aux_return_code_type *operation_result);
|
||
|
|
|
||
|
|
int dce_aux_transfer_dmub_raw(struct ddc_service *ddc,
|
||
|
|
struct aux_payload *payload,
|
||
|
|
enum aux_return_code_type *operation_result);
|
||
|
|
bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
|
||
|
|
struct aux_payload *cmd);
|
||
|
|
|
||
|
|
struct dce_aux_funcs {
|
||
|
|
uint32_t (*configure_timeout)
|
||
|
|
(struct ddc_service *ddc,
|
||
|
|
uint32_t timeout);
|
||
|
|
void (*destroy)
|
||
|
|
(struct aux_engine **ptr);
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif
|