44 lines
1.6 KiB
C
44 lines
1.6 KiB
C
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/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
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/* Copyright(c) 2014 - 2020 Intel Corporation */
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#ifndef ADF_C3XXX_HW_DATA_H_
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#define ADF_C3XXX_HW_DATA_H_
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/* PCIe configuration space */
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#define ADF_C3XXX_PMISC_BAR 0
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#define ADF_C3XXX_ETR_BAR 1
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#define ADF_C3XXX_RX_RINGS_OFFSET 8
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#define ADF_C3XXX_TX_RINGS_MASK 0xFF
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#define ADF_C3XXX_MAX_ACCELERATORS 3
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#define ADF_C3XXX_MAX_ACCELENGINES 6
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#define ADF_C3XXX_ACCELERATORS_REG_OFFSET 16
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#define ADF_C3XXX_ACCELERATORS_MASK 0x7
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#define ADF_C3XXX_ACCELENGINES_MASK 0x3F
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#define ADF_C3XXX_ETR_MAX_BANKS 16
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#define ADF_C3XXX_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
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#define ADF_C3XXX_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
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#define ADF_C3XXX_SMIA0_MASK 0xFFFF
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#define ADF_C3XXX_SMIA1_MASK 0x1
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#define ADF_C3XXX_SOFTSTRAP_CSR_OFFSET 0x2EC
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/* Error detection and correction */
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#define ADF_C3XXX_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818)
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#define ADF_C3XXX_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960)
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#define ADF_C3XXX_ENABLE_AE_ECC_ERR BIT(28)
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#define ADF_C3XXX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
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#define ADF_C3XXX_UERRSSMSH(i) (i * 0x4000 + 0x18)
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#define ADF_C3XXX_CERRSSMSH(i) (i * 0x4000 + 0x10)
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#define ADF_C3XXX_ERRSSMSH_EN BIT(3)
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#define ADF_C3XXX_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i) * 0x04))
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/* AE to function mapping */
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#define ADF_C3XXX_AE2FUNC_MAP_GRP_A_NUM_REGS 48
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#define ADF_C3XXX_AE2FUNC_MAP_GRP_B_NUM_REGS 6
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/* Firmware Binary */
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#define ADF_C3XXX_FW "qat_c3xxx.bin"
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#define ADF_C3XXX_MMP "qat_c3xxx_mmp.bin"
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void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data);
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void adf_clean_hw_data_c3xxx(struct adf_hw_device_data *hw_data);
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#endif
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