411 lines
10 KiB
C
411 lines
10 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/of_irq.h>
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#include <asm/pmac_feature.h>
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#include <asm/pmac_pfunc.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt...) printk(fmt)
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#else
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#define DBG(fmt...)
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#endif
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static irqreturn_t macio_gpio_irq(int irq, void *data)
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{
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pmf_do_irq(data);
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return IRQ_HANDLED;
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}
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static int macio_do_gpio_irq_enable(struct pmf_function *func)
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{
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unsigned int irq = irq_of_parse_and_map(func->node, 0);
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if (!irq)
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return -EINVAL;
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return request_irq(irq, macio_gpio_irq, 0, func->node->name, func);
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}
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static int macio_do_gpio_irq_disable(struct pmf_function *func)
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{
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unsigned int irq = irq_of_parse_and_map(func->node, 0);
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if (!irq)
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return -EINVAL;
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free_irq(irq, func);
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return 0;
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}
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static int macio_do_gpio_write(PMF_STD_ARGS, u8 value, u8 mask)
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{
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u8 __iomem *addr = (u8 __iomem *)func->driver_data;
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unsigned long flags;
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u8 tmp;
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/* Check polarity */
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if (args && args->count && !args->u[0].v)
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value = ~value;
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/* Toggle the GPIO */
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raw_spin_lock_irqsave(&feature_lock, flags);
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tmp = readb(addr);
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tmp = (tmp & ~mask) | (value & mask);
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DBG("Do write 0x%02x to GPIO %pOF (%p)\n",
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tmp, func->node, addr);
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writeb(tmp, addr);
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raw_spin_unlock_irqrestore(&feature_lock, flags);
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return 0;
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}
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static int macio_do_gpio_read(PMF_STD_ARGS, u8 mask, int rshift, u8 xor)
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{
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u8 __iomem *addr = (u8 __iomem *)func->driver_data;
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u32 value;
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/* Check if we have room for reply */
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if (args == NULL || args->count == 0 || args->u[0].p == NULL)
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return -EINVAL;
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value = readb(addr);
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*args->u[0].p = ((value & mask) >> rshift) ^ xor;
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return 0;
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}
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static int macio_do_delay(PMF_STD_ARGS, u32 duration)
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{
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/* assume we can sleep ! */
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msleep((duration + 999) / 1000);
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return 0;
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}
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static struct pmf_handlers macio_gpio_handlers = {
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.irq_enable = macio_do_gpio_irq_enable,
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.irq_disable = macio_do_gpio_irq_disable,
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.write_gpio = macio_do_gpio_write,
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.read_gpio = macio_do_gpio_read,
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.delay = macio_do_delay,
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};
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static void macio_gpio_init_one(struct macio_chip *macio)
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{
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struct device_node *gparent, *gp;
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/*
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* Find the "gpio" parent node
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*/
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for_each_child_of_node(macio->of_node, gparent)
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if (of_node_name_eq(gparent, "gpio"))
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break;
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if (gparent == NULL)
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return;
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DBG("Installing GPIO functions for macio %pOF\n",
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macio->of_node);
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/*
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* Ok, got one, we dont need anything special to track them down, so
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* we just create them all
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*/
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for_each_child_of_node(gparent, gp) {
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const u32 *reg = of_get_property(gp, "reg", NULL);
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unsigned long offset;
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if (reg == NULL)
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continue;
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offset = *reg;
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/* Deal with old style device-tree. We can safely hard code the
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* offset for now too even if it's a bit gross ...
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*/
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if (offset < 0x50)
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offset += 0x50;
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offset += (unsigned long)macio->base;
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pmf_register_driver(gp, &macio_gpio_handlers, (void *)offset);
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}
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DBG("Calling initial GPIO functions for macio %pOF\n",
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macio->of_node);
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/* And now we run all the init ones */
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for_each_child_of_node(gparent, gp)
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pmf_do_functions(gp, NULL, 0, PMF_FLAGS_ON_INIT, NULL);
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/* Note: We do not at this point implement the "at sleep" or "at wake"
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* functions. I yet to find any for GPIOs anyway
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*/
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}
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static int macio_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask)
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{
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struct macio_chip *macio = func->driver_data;
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unsigned long flags;
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raw_spin_lock_irqsave(&feature_lock, flags);
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MACIO_OUT32(offset, (MACIO_IN32(offset) & ~mask) | (value & mask));
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raw_spin_unlock_irqrestore(&feature_lock, flags);
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return 0;
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}
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static int macio_do_read_reg32(PMF_STD_ARGS, u32 offset)
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{
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struct macio_chip *macio = func->driver_data;
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/* Check if we have room for reply */
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if (args == NULL || args->count == 0 || args->u[0].p == NULL)
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return -EINVAL;
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*args->u[0].p = MACIO_IN32(offset);
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return 0;
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}
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static int macio_do_write_reg8(PMF_STD_ARGS, u32 offset, u8 value, u8 mask)
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{
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struct macio_chip *macio = func->driver_data;
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unsigned long flags;
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raw_spin_lock_irqsave(&feature_lock, flags);
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MACIO_OUT8(offset, (MACIO_IN8(offset) & ~mask) | (value & mask));
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raw_spin_unlock_irqrestore(&feature_lock, flags);
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return 0;
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}
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static int macio_do_read_reg8(PMF_STD_ARGS, u32 offset)
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{
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struct macio_chip *macio = func->driver_data;
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/* Check if we have room for reply */
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if (args == NULL || args->count == 0 || args->u[0].p == NULL)
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return -EINVAL;
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*((u8 *)(args->u[0].p)) = MACIO_IN8(offset);
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return 0;
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}
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static int macio_do_read_reg32_msrx(PMF_STD_ARGS, u32 offset, u32 mask,
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u32 shift, u32 xor)
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{
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struct macio_chip *macio = func->driver_data;
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/* Check if we have room for reply */
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if (args == NULL || args->count == 0 || args->u[0].p == NULL)
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return -EINVAL;
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*args->u[0].p = ((MACIO_IN32(offset) & mask) >> shift) ^ xor;
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return 0;
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}
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static int macio_do_read_reg8_msrx(PMF_STD_ARGS, u32 offset, u32 mask,
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u32 shift, u32 xor)
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{
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struct macio_chip *macio = func->driver_data;
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/* Check if we have room for reply */
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if (args == NULL || args->count == 0 || args->u[0].p == NULL)
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return -EINVAL;
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*((u8 *)(args->u[0].p)) = ((MACIO_IN8(offset) & mask) >> shift) ^ xor;
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return 0;
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}
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static int macio_do_write_reg32_slm(PMF_STD_ARGS, u32 offset, u32 shift,
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u32 mask)
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{
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struct macio_chip *macio = func->driver_data;
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unsigned long flags;
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u32 tmp, val;
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/* Check args */
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if (args == NULL || args->count == 0)
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return -EINVAL;
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raw_spin_lock_irqsave(&feature_lock, flags);
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tmp = MACIO_IN32(offset);
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val = args->u[0].v << shift;
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tmp = (tmp & ~mask) | (val & mask);
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MACIO_OUT32(offset, tmp);
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raw_spin_unlock_irqrestore(&feature_lock, flags);
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return 0;
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}
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static int macio_do_write_reg8_slm(PMF_STD_ARGS, u32 offset, u32 shift,
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u32 mask)
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{
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struct macio_chip *macio = func->driver_data;
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unsigned long flags;
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u32 tmp, val;
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/* Check args */
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if (args == NULL || args->count == 0)
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return -EINVAL;
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raw_spin_lock_irqsave(&feature_lock, flags);
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tmp = MACIO_IN8(offset);
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val = args->u[0].v << shift;
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tmp = (tmp & ~mask) | (val & mask);
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MACIO_OUT8(offset, tmp);
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raw_spin_unlock_irqrestore(&feature_lock, flags);
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return 0;
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}
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static struct pmf_handlers macio_mmio_handlers = {
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.write_reg32 = macio_do_write_reg32,
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.read_reg32 = macio_do_read_reg32,
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.write_reg8 = macio_do_write_reg8,
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.read_reg8 = macio_do_read_reg8,
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.read_reg32_msrx = macio_do_read_reg32_msrx,
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.read_reg8_msrx = macio_do_read_reg8_msrx,
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.write_reg32_slm = macio_do_write_reg32_slm,
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.write_reg8_slm = macio_do_write_reg8_slm,
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.delay = macio_do_delay,
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};
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static void macio_mmio_init_one(struct macio_chip *macio)
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{
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DBG("Installing MMIO functions for macio %pOF\n",
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macio->of_node);
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pmf_register_driver(macio->of_node, &macio_mmio_handlers, macio);
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}
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static struct device_node *unin_hwclock;
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static int unin_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&feature_lock, flags);
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/* This is fairly bogus in darwin, but it should work for our needs
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* implemeted that way:
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*/
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UN_OUT(offset, (UN_IN(offset) & ~mask) | (value & mask));
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raw_spin_unlock_irqrestore(&feature_lock, flags);
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return 0;
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}
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static struct pmf_handlers unin_mmio_handlers = {
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.write_reg32 = unin_do_write_reg32,
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.delay = macio_do_delay,
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};
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static void uninorth_install_pfunc(void)
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{
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struct device_node *np;
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DBG("Installing functions for UniN %pOF\n",
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uninorth_node);
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/*
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* Install handlers for the bridge itself
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*/
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pmf_register_driver(uninorth_node, &unin_mmio_handlers, NULL);
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pmf_do_functions(uninorth_node, NULL, 0, PMF_FLAGS_ON_INIT, NULL);
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/*
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* Install handlers for the hwclock child if any
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*/
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for (np = NULL; (np = of_get_next_child(uninorth_node, np)) != NULL;)
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if (of_node_name_eq(np, "hw-clock")) {
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unin_hwclock = np;
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break;
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}
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if (unin_hwclock) {
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DBG("Installing functions for UniN clock %pOF\n",
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unin_hwclock);
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pmf_register_driver(unin_hwclock, &unin_mmio_handlers, NULL);
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pmf_do_functions(unin_hwclock, NULL, 0, PMF_FLAGS_ON_INIT,
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NULL);
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}
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}
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/* We export this as the SMP code might init us early */
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int __init pmac_pfunc_base_install(void)
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{
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static int pfbase_inited;
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int i;
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if (pfbase_inited)
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return 0;
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pfbase_inited = 1;
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if (!machine_is(powermac))
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return 0;
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DBG("Installing base platform functions...\n");
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/*
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* Locate mac-io chips and install handlers
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*/
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for (i = 0 ; i < MAX_MACIO_CHIPS; i++) {
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if (macio_chips[i].of_node) {
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macio_mmio_init_one(&macio_chips[i]);
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macio_gpio_init_one(&macio_chips[i]);
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}
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}
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/*
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* Install handlers for northbridge and direct mapped hwclock
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* if any. We do not implement the config space access callback
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* which is only ever used for functions that we do not call in
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* the current driver (enabling/disabling cells in U2, mostly used
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* to restore the PCI settings, we do that differently)
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*/
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if (uninorth_node && uninorth_base)
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uninorth_install_pfunc();
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DBG("All base functions installed\n");
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return 0;
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}
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machine_arch_initcall(powermac, pmac_pfunc_base_install);
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#ifdef CONFIG_PM
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/* Those can be called by pmac_feature. Ultimately, I should use a sysdev
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|
* or a device, but for now, that's good enough until I sort out some
|
||
|
|
* ordering issues. Also, we do not bother with GPIOs, as so far I yet have
|
||
|
|
* to see a case where a GPIO function has the on-suspend or on-resume bit
|
||
|
|
*/
|
||
|
|
void pmac_pfunc_base_suspend(void)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
for (i = 0 ; i < MAX_MACIO_CHIPS; i++) {
|
||
|
|
if (macio_chips[i].of_node)
|
||
|
|
pmf_do_functions(macio_chips[i].of_node, NULL, 0,
|
||
|
|
PMF_FLAGS_ON_SLEEP, NULL);
|
||
|
|
}
|
||
|
|
if (uninorth_node)
|
||
|
|
pmf_do_functions(uninorth_node, NULL, 0,
|
||
|
|
PMF_FLAGS_ON_SLEEP, NULL);
|
||
|
|
if (unin_hwclock)
|
||
|
|
pmf_do_functions(unin_hwclock, NULL, 0,
|
||
|
|
PMF_FLAGS_ON_SLEEP, NULL);
|
||
|
|
}
|
||
|
|
|
||
|
|
void pmac_pfunc_base_resume(void)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
if (unin_hwclock)
|
||
|
|
pmf_do_functions(unin_hwclock, NULL, 0,
|
||
|
|
PMF_FLAGS_ON_WAKE, NULL);
|
||
|
|
if (uninorth_node)
|
||
|
|
pmf_do_functions(uninorth_node, NULL, 0,
|
||
|
|
PMF_FLAGS_ON_WAKE, NULL);
|
||
|
|
for (i = 0 ; i < MAX_MACIO_CHIPS; i++) {
|
||
|
|
if (macio_chips[i].of_node)
|
||
|
|
pmf_do_functions(macio_chips[i].of_node, NULL, 0,
|
||
|
|
PMF_FLAGS_ON_WAKE, NULL);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* CONFIG_PM */
|