318 lines
9.7 KiB
C
318 lines
9.7 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* FSP-2 board specific routines
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*
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* Based on earlier code:
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* Matt Porter <mporter@kernel.crashing.org>
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* Copyright 2002-2005 MontaVista Software Inc.
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*
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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* Copyright (c) 2003-2005 Zultys Technologies
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*
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* Rewritten and ported to the merged powerpc tree:
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* Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
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*/
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#include <linux/init.h>
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#include <linux/of_platform.h>
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#include <linux/rtc.h>
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#include <asm/machdep.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <asm/time.h>
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#include <asm/uic.h>
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#include <asm/ppc4xx.h>
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#include <asm/dcr.h>
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#include <linux/interrupt.h>
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#include <linux/of_irq.h>
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#include "fsp2.h"
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#define FSP2_BUS_ERR "ibm,bus-error-irq"
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#define FSP2_CMU_ERR "ibm,cmu-error-irq"
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#define FSP2_CONF_ERR "ibm,conf-error-irq"
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#define FSP2_OPBD_ERR "ibm,opbd-error-irq"
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#define FSP2_MCUE "ibm,mc-ue-irq"
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#define FSP2_RST_WRN "ibm,reset-warning-irq"
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static __initdata struct of_device_id fsp2_of_bus[] = {
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{ .compatible = "ibm,plb4", },
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{ .compatible = "ibm,plb6", },
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{ .compatible = "ibm,opb", },
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{},
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};
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static void l2regs(void)
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{
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pr_err("L2 Controller:\n");
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pr_err("MCK: 0x%08x\n", mfl2(L2MCK));
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pr_err("INT: 0x%08x\n", mfl2(L2INT));
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pr_err("PLBSTAT0: 0x%08x\n", mfl2(L2PLBSTAT0));
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pr_err("PLBSTAT1: 0x%08x\n", mfl2(L2PLBSTAT1));
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pr_err("ARRSTAT0: 0x%08x\n", mfl2(L2ARRSTAT0));
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pr_err("ARRSTAT1: 0x%08x\n", mfl2(L2ARRSTAT1));
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pr_err("ARRSTAT2: 0x%08x\n", mfl2(L2ARRSTAT2));
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pr_err("CPUSTAT: 0x%08x\n", mfl2(L2CPUSTAT));
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pr_err("RACSTAT0: 0x%08x\n", mfl2(L2RACSTAT0));
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pr_err("WACSTAT0: 0x%08x\n", mfl2(L2WACSTAT0));
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pr_err("WACSTAT1: 0x%08x\n", mfl2(L2WACSTAT1));
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pr_err("WACSTAT2: 0x%08x\n", mfl2(L2WACSTAT2));
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pr_err("WDFSTAT: 0x%08x\n", mfl2(L2WDFSTAT));
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pr_err("LOG0: 0x%08x\n", mfl2(L2LOG0));
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pr_err("LOG1: 0x%08x\n", mfl2(L2LOG1));
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pr_err("LOG2: 0x%08x\n", mfl2(L2LOG2));
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pr_err("LOG3: 0x%08x\n", mfl2(L2LOG3));
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pr_err("LOG4: 0x%08x\n", mfl2(L2LOG4));
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pr_err("LOG5: 0x%08x\n", mfl2(L2LOG5));
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}
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static void show_plbopb_regs(u32 base, int num)
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{
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pr_err("\nPLBOPB Bridge %d:\n", num);
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pr_err("GESR0: 0x%08x\n", mfdcr(base + PLB4OPB_GESR0));
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pr_err("GESR1: 0x%08x\n", mfdcr(base + PLB4OPB_GESR1));
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pr_err("GESR2: 0x%08x\n", mfdcr(base + PLB4OPB_GESR2));
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pr_err("GEARU: 0x%08x\n", mfdcr(base + PLB4OPB_GEARU));
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pr_err("GEAR: 0x%08x\n", mfdcr(base + PLB4OPB_GEAR));
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}
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static irqreturn_t bus_err_handler(int irq, void *data)
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{
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pr_err("Bus Error\n");
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l2regs();
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pr_err("\nPLB6 Controller:\n");
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pr_err("BC_SHD: 0x%08x\n", mfdcr(DCRN_PLB6_SHD));
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pr_err("BC_ERR: 0x%08x\n", mfdcr(DCRN_PLB6_ERR));
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pr_err("\nPLB6-to-PLB4 Bridge:\n");
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pr_err("ESR: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_ESR));
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pr_err("EARH: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_EARH));
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pr_err("EARL: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_EARL));
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pr_err("\nPLB4-to-PLB6 Bridge:\n");
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pr_err("ESR: 0x%08x\n", mfdcr(DCRN_PLB4PLB6_ESR));
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pr_err("EARH: 0x%08x\n", mfdcr(DCRN_PLB4PLB6_EARH));
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pr_err("EARL: 0x%08x\n", mfdcr(DCRN_PLB4PLB6_EARL));
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pr_err("\nPLB6-to-MCIF Bridge:\n");
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pr_err("BESR0: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BESR0));
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pr_err("BESR1: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BESR1));
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pr_err("BEARH: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BEARH));
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pr_err("BEARL: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BEARL));
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pr_err("\nPLB4 Arbiter:\n");
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pr_err("P0ESRH 0x%08x\n", mfdcr(DCRN_PLB4_P0ESRH));
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pr_err("P0ESRL 0x%08x\n", mfdcr(DCRN_PLB4_P0ESRL));
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pr_err("P0EARH 0x%08x\n", mfdcr(DCRN_PLB4_P0EARH));
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pr_err("P0EARH 0x%08x\n", mfdcr(DCRN_PLB4_P0EARH));
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pr_err("P1ESRH 0x%08x\n", mfdcr(DCRN_PLB4_P1ESRH));
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pr_err("P1ESRL 0x%08x\n", mfdcr(DCRN_PLB4_P1ESRL));
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pr_err("P1EARH 0x%08x\n", mfdcr(DCRN_PLB4_P1EARH));
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pr_err("P1EARH 0x%08x\n", mfdcr(DCRN_PLB4_P1EARH));
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show_plbopb_regs(DCRN_PLB4OPB0_BASE, 0);
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show_plbopb_regs(DCRN_PLB4OPB1_BASE, 1);
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show_plbopb_regs(DCRN_PLB4OPB2_BASE, 2);
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show_plbopb_regs(DCRN_PLB4OPB3_BASE, 3);
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pr_err("\nPLB4-to-AHB Bridge:\n");
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pr_err("ESR: 0x%08x\n", mfdcr(DCRN_PLB4AHB_ESR));
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pr_err("SEUAR: 0x%08x\n", mfdcr(DCRN_PLB4AHB_SEUAR));
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pr_err("SELAR: 0x%08x\n", mfdcr(DCRN_PLB4AHB_SELAR));
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pr_err("\nAHB-to-PLB4 Bridge:\n");
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pr_err("\nESR: 0x%08x\n", mfdcr(DCRN_AHBPLB4_ESR));
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pr_err("\nEAR: 0x%08x\n", mfdcr(DCRN_AHBPLB4_EAR));
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panic("Bus Error\n");
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}
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static irqreturn_t cmu_err_handler(int irq, void *data) {
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pr_err("CMU Error\n");
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pr_err("FIR0: 0x%08x\n", mfcmu(CMUN_FIR0));
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panic("CMU Error\n");
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}
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static irqreturn_t conf_err_handler(int irq, void *data) {
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pr_err("Configuration Logic Error\n");
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pr_err("CONF_FIR: 0x%08x\n", mfdcr(DCRN_CONF_FIR_RWC));
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pr_err("RPERR0: 0x%08x\n", mfdcr(DCRN_CONF_RPERR0));
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pr_err("RPERR1: 0x%08x\n", mfdcr(DCRN_CONF_RPERR1));
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panic("Configuration Logic Error\n");
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}
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static irqreturn_t opbd_err_handler(int irq, void *data) {
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panic("OPBD Error\n");
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}
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static irqreturn_t mcue_handler(int irq, void *data) {
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pr_err("DDR: Uncorrectable Error\n");
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pr_err("MCSTAT: 0x%08x\n",
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mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCSTAT));
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pr_err("MCOPT1: 0x%08x\n",
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mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCOPT1));
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pr_err("MCOPT2: 0x%08x\n",
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mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCOPT2));
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pr_err("PHYSTAT: 0x%08x\n",
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mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_PHYSTAT));
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pr_err("CFGR0: 0x%08x\n",
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mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR0));
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pr_err("CFGR1: 0x%08x\n",
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mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR1));
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pr_err("CFGR2: 0x%08x\n",
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mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR2));
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pr_err("CFGR3: 0x%08x\n",
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mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR3));
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pr_err("SCRUB_CNTL: 0x%08x\n",
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mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_SCRUB_CNTL));
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pr_err("ECCERR_PORT0: 0x%08x\n",
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mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_PORT0));
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pr_err("ECCERR_ADDR_PORT0: 0x%08x\n",
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mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_ADDR_PORT0));
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pr_err("ECCERR_CNT_PORT0: 0x%08x\n",
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mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_COUNT_PORT0));
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pr_err("ECC_CHECK_PORT0: 0x%08x\n",
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mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECC_CHECK_PORT0));
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pr_err("MCER0: 0x%08x\n",
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mfdcr(DCRN_CW_BASE + DCRN_CW_MCER0));
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pr_err("MCER1: 0x%08x\n",
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mfdcr(DCRN_CW_BASE + DCRN_CW_MCER1));
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pr_err("BESR: 0x%08x\n",
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mfdcr(DCRN_PLB6MCIF_BESR0));
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pr_err("BEARL: 0x%08x\n",
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mfdcr(DCRN_PLB6MCIF_BEARL));
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pr_err("BEARH: 0x%08x\n",
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mfdcr(DCRN_PLB6MCIF_BEARH));
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panic("DDR: Uncorrectable Error\n");
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}
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static irqreturn_t rst_wrn_handler(int irq, void *data) {
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u32 crcs = mfcmu(CMUN_CRCS);
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switch (crcs & CRCS_STAT_MASK) {
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case CRCS_STAT_CHIP_RST_B:
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panic("Received chassis-initiated reset request");
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default:
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panic("Unknown external reset: CRCS=0x%x", crcs);
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}
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}
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static void node_irq_request(const char *compat, irq_handler_t errirq_handler)
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{
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struct device_node *np;
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unsigned int irq;
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int32_t rc;
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for_each_compatible_node(np, NULL, compat) {
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irq = irq_of_parse_and_map(np, 0);
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if (irq == NO_IRQ) {
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pr_err("device tree node %pOFn is missing a interrupt",
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np);
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of_node_put(np);
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return;
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}
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rc = request_irq(irq, errirq_handler, 0, np->name, np);
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if (rc) {
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pr_err("fsp_of_probe: request_irq failed: np=%pOF rc=%d",
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np, rc);
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of_node_put(np);
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return;
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}
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}
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}
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static void critical_irq_setup(void)
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{
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node_irq_request(FSP2_CMU_ERR, cmu_err_handler);
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node_irq_request(FSP2_BUS_ERR, bus_err_handler);
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node_irq_request(FSP2_CONF_ERR, conf_err_handler);
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node_irq_request(FSP2_OPBD_ERR, opbd_err_handler);
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node_irq_request(FSP2_MCUE, mcue_handler);
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node_irq_request(FSP2_RST_WRN, rst_wrn_handler);
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}
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static int __init fsp2_device_probe(void)
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{
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of_platform_bus_probe(NULL, fsp2_of_bus, NULL);
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return 0;
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}
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machine_device_initcall(fsp2, fsp2_device_probe);
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static int __init fsp2_probe(void)
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{
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u32 val;
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unsigned long root = of_get_flat_dt_root();
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if (!of_flat_dt_is_compatible(root, "ibm,fsp2"))
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return 0;
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/* Clear BC_ERR and mask snoopable request plb errors. */
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val = mfdcr(DCRN_PLB6_CR0);
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val |= 0x20000000;
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mtdcr(DCRN_PLB6_BASE, val);
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mtdcr(DCRN_PLB6_HD, 0xffff0000);
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mtdcr(DCRN_PLB6_SHD, 0xffff0000);
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/* TVSENSE reset is blocked (clock gated) by the POR default of the TVS
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* sleep config bit. As a consequence, TVSENSE will provide erratic
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* sensor values, which may result in spurious (parity) errors
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* recorded in the CMU FIR and leading to erroneous interrupt requests
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* once the CMU interrupt is unmasked.
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*/
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/* 1. set TVS1[UNDOZE] */
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val = mfcmu(CMUN_TVS1);
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val |= 0x4;
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mtcmu(CMUN_TVS1, val);
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/* 2. clear FIR[TVS] and FIR[TVSPAR] */
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val = mfcmu(CMUN_FIR0);
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val |= 0x30000000;
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mtcmu(CMUN_FIR0, val);
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/* L2 machine checks */
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mtl2(L2PLBMCKEN0, 0xffffffff);
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mtl2(L2PLBMCKEN1, 0x0000ffff);
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mtl2(L2ARRMCKEN0, 0xffffffff);
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mtl2(L2ARRMCKEN1, 0xffffffff);
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mtl2(L2ARRMCKEN2, 0xfffff000);
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mtl2(L2CPUMCKEN, 0xffffffff);
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mtl2(L2RACMCKEN0, 0xffffffff);
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mtl2(L2WACMCKEN0, 0xffffffff);
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mtl2(L2WACMCKEN1, 0xffffffff);
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mtl2(L2WACMCKEN2, 0xffffffff);
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mtl2(L2WDFMCKEN, 0xffffffff);
|
||
|
|
|
||
|
|
/* L2 interrupts */
|
||
|
|
mtl2(L2PLBINTEN1, 0xffff0000);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* At a global level, enable all L2 machine checks and interrupts
|
||
|
|
* reported by the L2 subsystems, except for the external machine check
|
||
|
|
* input (UIC0.1).
|
||
|
|
*/
|
||
|
|
mtl2(L2MCKEN, 0x000007ff);
|
||
|
|
mtl2(L2INTEN, 0x000004ff);
|
||
|
|
|
||
|
|
/* Enable FSP-2 configuration logic parity errors */
|
||
|
|
mtdcr(DCRN_CONF_EIR_RS, 0x80000000);
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __init fsp2_irq_init(void)
|
||
|
|
{
|
||
|
|
uic_init_tree();
|
||
|
|
critical_irq_setup();
|
||
|
|
}
|
||
|
|
|
||
|
|
define_machine(fsp2) {
|
||
|
|
.name = "FSP-2",
|
||
|
|
.probe = fsp2_probe,
|
||
|
|
.progress = udbg_progress,
|
||
|
|
.init_IRQ = fsp2_irq_init,
|
||
|
|
.get_irq = uic_get_irq,
|
||
|
|
.restart = ppc4xx_reset_system,
|
||
|
|
.calibrate_decr = generic_calibrate_decr,
|
||
|
|
};
|