413 lines
10 KiB
ArmAsm
413 lines
10 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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*
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* Copyright SUSE Linux Products GmbH 2010
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*
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* Authors: Alexander Graf <agraf@suse.de>
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*/
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/* Real mode helpers */
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#include <asm/asm-compat.h>
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#include <asm/feature-fixups.h>
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#if defined(CONFIG_PPC_BOOK3S_64)
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#define GET_SHADOW_VCPU(reg) \
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mr reg, r13
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#elif defined(CONFIG_PPC_BOOK3S_32)
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#define GET_SHADOW_VCPU(reg) \
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tophys(reg, r2); \
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lwz reg, (THREAD + THREAD_KVM_SVCPU)(reg); \
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tophys(reg, reg)
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#endif
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/* Disable for nested KVM */
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#define USE_QUICK_LAST_INST
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/* Get helper functions for subarch specific functionality */
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#if defined(CONFIG_PPC_BOOK3S_64)
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#include "book3s_64_slb.S"
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#elif defined(CONFIG_PPC_BOOK3S_32)
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#include "book3s_32_sr.S"
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#endif
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/******************************************************************************
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* *
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* Entry code *
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* *
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*****************************************************************************/
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.global kvmppc_handler_trampoline_enter
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kvmppc_handler_trampoline_enter:
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/* Required state:
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*
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* MSR = ~IR|DR
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* R1 = host R1
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* R2 = host R2
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* R4 = guest shadow MSR
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* R5 = normal host MSR
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* R6 = current host MSR (EE, IR, DR off)
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* LR = highmem guest exit code
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* all other volatile GPRS = free
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* SVCPU[CR] = guest CR
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* SVCPU[XER] = guest XER
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* SVCPU[CTR] = guest CTR
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* SVCPU[LR] = guest LR
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*/
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/* r3 = shadow vcpu */
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GET_SHADOW_VCPU(r3)
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/* Save guest exit handler address and MSR */
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mflr r0
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PPC_STL r0, HSTATE_VMHANDLER(r3)
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PPC_STL r5, HSTATE_HOST_MSR(r3)
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/* Save R1/R2 in the PACA (64-bit) or shadow_vcpu (32-bit) */
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PPC_STL r1, HSTATE_HOST_R1(r3)
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PPC_STL r2, HSTATE_HOST_R2(r3)
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/* Activate guest mode, so faults get handled by KVM */
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li r11, KVM_GUEST_MODE_GUEST
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stb r11, HSTATE_IN_GUEST(r3)
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/* Switch to guest segment. This is subarch specific. */
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LOAD_GUEST_SEGMENTS
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#ifdef CONFIG_PPC_BOOK3S_64
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BEGIN_FTR_SECTION
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/* Save host FSCR */
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mfspr r8, SPRN_FSCR
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std r8, HSTATE_HOST_FSCR(r13)
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/* Set FSCR during guest execution */
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ld r9, SVCPU_SHADOW_FSCR(r13)
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mtspr SPRN_FSCR, r9
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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/* Some guests may need to have dcbz set to 32 byte length.
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*
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* Usually we ensure that by patching the guest's instructions
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* to trap on dcbz and emulate it in the hypervisor.
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*
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* If we can, we should tell the CPU to use 32 byte dcbz though,
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* because that's a lot faster.
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*/
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lbz r0, HSTATE_RESTORE_HID5(r3)
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cmpwi r0, 0
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beq no_dcbz32_on
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mfspr r0,SPRN_HID5
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ori r0, r0, 0x80 /* XXX HID5_dcbz32 = 0x80 */
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mtspr SPRN_HID5,r0
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no_dcbz32_on:
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#endif /* CONFIG_PPC_BOOK3S_64 */
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/* Enter guest */
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PPC_LL r8, SVCPU_CTR(r3)
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PPC_LL r9, SVCPU_LR(r3)
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lwz r10, SVCPU_CR(r3)
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PPC_LL r11, SVCPU_XER(r3)
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mtctr r8
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mtlr r9
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mtcr r10
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mtxer r11
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/* Move SRR0 and SRR1 into the respective regs */
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PPC_LL r9, SVCPU_PC(r3)
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/* First clear RI in our current MSR value */
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li r0, MSR_RI
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andc r6, r6, r0
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PPC_LL r0, SVCPU_R0(r3)
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PPC_LL r1, SVCPU_R1(r3)
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PPC_LL r2, SVCPU_R2(r3)
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PPC_LL r5, SVCPU_R5(r3)
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PPC_LL r7, SVCPU_R7(r3)
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PPC_LL r8, SVCPU_R8(r3)
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PPC_LL r10, SVCPU_R10(r3)
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PPC_LL r11, SVCPU_R11(r3)
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PPC_LL r12, SVCPU_R12(r3)
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PPC_LL r13, SVCPU_R13(r3)
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MTMSR_EERI(r6)
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mtsrr0 r9
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mtsrr1 r4
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PPC_LL r4, SVCPU_R4(r3)
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PPC_LL r6, SVCPU_R6(r3)
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PPC_LL r9, SVCPU_R9(r3)
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PPC_LL r3, (SVCPU_R3)(r3)
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RFI_TO_GUEST
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kvmppc_handler_trampoline_enter_end:
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/******************************************************************************
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* *
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* Exit code *
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* *
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*****************************************************************************/
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.global kvmppc_interrupt_pr
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kvmppc_interrupt_pr:
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/* 64-bit entry. Register usage at this point:
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*
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* SPRG_SCRATCH0 = guest R13
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* R9 = HSTATE_IN_GUEST
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* R12 = (guest CR << 32) | exit handler id
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* R13 = PACA
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* HSTATE.SCRATCH0 = guest R12
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* HSTATE.SCRATCH2 = guest R9
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*/
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#ifdef CONFIG_PPC64
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/* Match 32-bit entry */
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ld r9,HSTATE_SCRATCH2(r13)
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rotldi r12, r12, 32 /* Flip R12 halves for stw */
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stw r12, HSTATE_SCRATCH1(r13) /* CR is now in the low half */
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srdi r12, r12, 32 /* shift trap into low half */
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#endif
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.global kvmppc_handler_trampoline_exit
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kvmppc_handler_trampoline_exit:
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/* Register usage at this point:
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*
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* SPRG_SCRATCH0 = guest R13
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* R12 = exit handler id
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* R13 = shadow vcpu (32-bit) or PACA (64-bit)
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* HSTATE.SCRATCH0 = guest R12
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* HSTATE.SCRATCH1 = guest CR
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*/
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/* Save registers */
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PPC_STL r0, SVCPU_R0(r13)
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PPC_STL r1, SVCPU_R1(r13)
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PPC_STL r2, SVCPU_R2(r13)
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PPC_STL r3, SVCPU_R3(r13)
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PPC_STL r4, SVCPU_R4(r13)
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PPC_STL r5, SVCPU_R5(r13)
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PPC_STL r6, SVCPU_R6(r13)
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PPC_STL r7, SVCPU_R7(r13)
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PPC_STL r8, SVCPU_R8(r13)
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PPC_STL r9, SVCPU_R9(r13)
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PPC_STL r10, SVCPU_R10(r13)
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PPC_STL r11, SVCPU_R11(r13)
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/* Restore R1/R2 so we can handle faults */
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PPC_LL r1, HSTATE_HOST_R1(r13)
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PPC_LL r2, HSTATE_HOST_R2(r13)
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/* Save guest PC and MSR */
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#ifdef CONFIG_PPC64
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BEGIN_FTR_SECTION
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andi. r0, r12, 0x2
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cmpwi cr1, r0, 0
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beq 1f
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mfspr r3,SPRN_HSRR0
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mfspr r4,SPRN_HSRR1
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andi. r12,r12,0x3ffd
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b 2f
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END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
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#endif
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1: mfsrr0 r3
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mfsrr1 r4
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2:
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PPC_STL r3, SVCPU_PC(r13)
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PPC_STL r4, SVCPU_SHADOW_SRR1(r13)
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/* Get scratch'ed off registers */
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GET_SCRATCH0(r9)
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PPC_LL r8, HSTATE_SCRATCH0(r13)
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lwz r7, HSTATE_SCRATCH1(r13)
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PPC_STL r9, SVCPU_R13(r13)
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PPC_STL r8, SVCPU_R12(r13)
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stw r7, SVCPU_CR(r13)
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/* Save more register state */
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mfxer r5
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mfdar r6
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mfdsisr r7
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mfctr r8
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mflr r9
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PPC_STL r5, SVCPU_XER(r13)
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PPC_STL r6, SVCPU_FAULT_DAR(r13)
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stw r7, SVCPU_FAULT_DSISR(r13)
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PPC_STL r8, SVCPU_CTR(r13)
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PPC_STL r9, SVCPU_LR(r13)
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/*
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* In order for us to easily get the last instruction,
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* we got the #vmexit at, we exploit the fact that the
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* virtual layout is still the same here, so we can just
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* ld from the guest's PC address
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*/
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/* We only load the last instruction when it's safe */
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cmpwi r12, BOOK3S_INTERRUPT_DATA_STORAGE
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beq ld_last_inst
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cmpwi r12, BOOK3S_INTERRUPT_PROGRAM
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beq ld_last_inst
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cmpwi r12, BOOK3S_INTERRUPT_SYSCALL
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beq ld_last_prev_inst
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cmpwi r12, BOOK3S_INTERRUPT_ALIGNMENT
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beq- ld_last_inst
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#ifdef CONFIG_PPC64
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BEGIN_FTR_SECTION
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cmpwi r12, BOOK3S_INTERRUPT_H_EMUL_ASSIST
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beq- ld_last_inst
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END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
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BEGIN_FTR_SECTION
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cmpwi r12, BOOK3S_INTERRUPT_FAC_UNAVAIL
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beq- ld_last_inst
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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#endif
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b no_ld_last_inst
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ld_last_prev_inst:
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addi r3, r3, -4
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ld_last_inst:
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/* Save off the guest instruction we're at */
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/* In case lwz faults */
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li r0, KVM_INST_FETCH_FAILED
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#ifdef USE_QUICK_LAST_INST
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/* Set guest mode to 'jump over instruction' so if lwz faults
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* we'll just continue at the next IP. */
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li r9, KVM_GUEST_MODE_SKIP
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stb r9, HSTATE_IN_GUEST(r13)
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/* 1) enable paging for data */
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mfmsr r9
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ori r11, r9, MSR_DR /* Enable paging for data */
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mtmsr r11
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sync
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/* 2) fetch the instruction */
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lwz r0, 0(r3)
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/* 3) disable paging again */
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mtmsr r9
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sync
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#endif
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stw r0, SVCPU_LAST_INST(r13)
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no_ld_last_inst:
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/* Unset guest mode */
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li r9, KVM_GUEST_MODE_NONE
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stb r9, HSTATE_IN_GUEST(r13)
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/* Switch back to host MMU */
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LOAD_HOST_SEGMENTS
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#ifdef CONFIG_PPC_BOOK3S_64
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lbz r5, HSTATE_RESTORE_HID5(r13)
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cmpwi r5, 0
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beq no_dcbz32_off
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li r4, 0
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mfspr r5,SPRN_HID5
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rldimi r5,r4,6,56
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mtspr SPRN_HID5,r5
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no_dcbz32_off:
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BEGIN_FTR_SECTION
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/* Save guest FSCR on a FAC_UNAVAIL interrupt */
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cmpwi r12, BOOK3S_INTERRUPT_FAC_UNAVAIL
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bne+ no_fscr_save
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mfspr r7, SPRN_FSCR
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std r7, SVCPU_SHADOW_FSCR(r13)
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no_fscr_save:
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/* Restore host FSCR */
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ld r8, HSTATE_HOST_FSCR(r13)
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mtspr SPRN_FSCR, r8
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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#endif /* CONFIG_PPC_BOOK3S_64 */
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/*
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* For some interrupts, we need to call the real Linux
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* handler, so it can do work for us. This has to happen
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* as if the interrupt arrived from the kernel though,
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* so let's fake it here where most state is restored.
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*
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* Having set up SRR0/1 with the address where we want
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* to continue with relocation on (potentially in module
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* space), we either just go straight there with rfi[d],
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* or we jump to an interrupt handler if there is an
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* interrupt to be handled first. In the latter case,
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* the rfi[d] at the end of the interrupt handler will
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* get us back to where we want to continue.
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*/
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/* Register usage at this point:
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|
|
*
|
||
|
|
* R1 = host R1
|
||
|
|
* R2 = host R2
|
||
|
|
* R10 = raw exit handler id
|
||
|
|
* R12 = exit handler id
|
||
|
|
* R13 = shadow vcpu (32-bit) or PACA (64-bit)
|
||
|
|
* SVCPU.* = guest *
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
|
||
|
|
PPC_LL r6, HSTATE_HOST_MSR(r13)
|
||
|
|
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
||
|
|
/*
|
||
|
|
* We don't want to change MSR[TS] bits via rfi here.
|
||
|
|
* The actual TM handling logic will be in host with
|
||
|
|
* recovered DR/IR bits after HSTATE_VMHANDLER.
|
||
|
|
* And MSR_TM can be enabled in HOST_MSR so rfid may
|
||
|
|
* not suppress this change and can lead to exception.
|
||
|
|
* Manually set MSR to prevent TS state change here.
|
||
|
|
*/
|
||
|
|
mfmsr r7
|
||
|
|
rldicl r7, r7, 64 - MSR_TS_S_LG, 62
|
||
|
|
rldimi r6, r7, MSR_TS_S_LG, 63 - MSR_TS_T_LG
|
||
|
|
#endif
|
||
|
|
PPC_LL r8, HSTATE_VMHANDLER(r13)
|
||
|
|
|
||
|
|
#ifdef CONFIG_PPC64
|
||
|
|
BEGIN_FTR_SECTION
|
||
|
|
beq cr1, 1f
|
||
|
|
mtspr SPRN_HSRR1, r6
|
||
|
|
mtspr SPRN_HSRR0, r8
|
||
|
|
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
|
||
|
|
#endif
|
||
|
|
1: /* Restore host msr -> SRR1 */
|
||
|
|
mtsrr1 r6
|
||
|
|
/* Load highmem handler address */
|
||
|
|
mtsrr0 r8
|
||
|
|
|
||
|
|
/* RFI into the highmem handler, or jump to interrupt handler */
|
||
|
|
cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
|
||
|
|
beqa BOOK3S_INTERRUPT_EXTERNAL
|
||
|
|
cmpwi r12, BOOK3S_INTERRUPT_DECREMENTER
|
||
|
|
beqa BOOK3S_INTERRUPT_DECREMENTER
|
||
|
|
cmpwi r12, BOOK3S_INTERRUPT_PERFMON
|
||
|
|
beqa BOOK3S_INTERRUPT_PERFMON
|
||
|
|
cmpwi r12, BOOK3S_INTERRUPT_DOORBELL
|
||
|
|
beqa BOOK3S_INTERRUPT_DOORBELL
|
||
|
|
|
||
|
|
RFI_TO_KERNEL
|
||
|
|
kvmppc_handler_trampoline_exit_end:
|