301 lines
8.1 KiB
C
301 lines
8.1 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Coldfire generic GPIO support.
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*
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* (C) Copyright 2009, Steven King <sfking@fdwdc.com>
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*/
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#ifndef mcfgpio_h
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#define mcfgpio_h
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#ifdef CONFIG_GPIOLIB
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#include <asm-generic/gpio.h>
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#else
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int __mcfgpio_get_value(unsigned gpio);
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void __mcfgpio_set_value(unsigned gpio, int value);
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int __mcfgpio_direction_input(unsigned gpio);
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int __mcfgpio_direction_output(unsigned gpio, int value);
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int __mcfgpio_request(unsigned gpio);
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void __mcfgpio_free(unsigned gpio);
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/* our alternate 'gpiolib' functions */
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static inline int __gpio_get_value(unsigned gpio)
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{
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if (gpio < MCFGPIO_PIN_MAX)
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return __mcfgpio_get_value(gpio);
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else
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return -EINVAL;
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}
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static inline void __gpio_set_value(unsigned gpio, int value)
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{
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if (gpio < MCFGPIO_PIN_MAX)
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__mcfgpio_set_value(gpio, value);
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}
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static inline int __gpio_cansleep(unsigned gpio)
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{
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if (gpio < MCFGPIO_PIN_MAX)
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return 0;
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else
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return -EINVAL;
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}
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static inline int __gpio_to_irq(unsigned gpio)
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{
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return -EINVAL;
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}
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static inline int gpio_direction_input(unsigned gpio)
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{
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if (gpio < MCFGPIO_PIN_MAX)
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return __mcfgpio_direction_input(gpio);
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else
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return -EINVAL;
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}
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static inline int gpio_direction_output(unsigned gpio, int value)
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{
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if (gpio < MCFGPIO_PIN_MAX)
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return __mcfgpio_direction_output(gpio, value);
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else
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return -EINVAL;
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}
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static inline int gpio_request(unsigned gpio, const char *label)
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{
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if (gpio < MCFGPIO_PIN_MAX)
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return __mcfgpio_request(gpio);
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else
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return -EINVAL;
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}
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static inline void gpio_free(unsigned gpio)
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{
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if (gpio < MCFGPIO_PIN_MAX)
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__mcfgpio_free(gpio);
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}
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#endif /* CONFIG_GPIOLIB */
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/*
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* The Freescale Coldfire family is quite varied in how they implement GPIO.
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* Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
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* only one port, others have multiple ports; some have a single data latch
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* for both input and output, others have a separate pin data register to read
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* input; some require a read-modify-write access to change an output, others
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* have set and clear registers for some of the outputs; Some have all the
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* GPIOs in a single control area, others have some GPIOs implemented in
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* different modules.
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*
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* This implementation attempts accommodate the differences while presenting
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* a generic interface that will optimize to as few instructions as possible.
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*/
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#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
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defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
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defined(CONFIG_M5441x)
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/* These parts have GPIO organized by 8 bit ports */
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#define MCFGPIO_PORTTYPE u8
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#define MCFGPIO_PORTSIZE 8
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#define mcfgpio_read(port) __raw_readb(port)
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#define mcfgpio_write(data, port) __raw_writeb(data, port)
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#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
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/* These parts have GPIO organized by 16 bit ports */
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#define MCFGPIO_PORTTYPE u16
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#define MCFGPIO_PORTSIZE 16
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#define mcfgpio_read(port) __raw_readw(port)
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#define mcfgpio_write(data, port) __raw_writew(data, port)
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#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
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/* These parts have GPIO organized by 32 bit ports */
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#define MCFGPIO_PORTTYPE u32
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#define MCFGPIO_PORTSIZE 32
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#define mcfgpio_read(port) __raw_readl(port)
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#define mcfgpio_write(data, port) __raw_writel(data, port)
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#endif
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#define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
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#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
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#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
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defined(CONFIG_M5441x)
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/*
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* These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
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* read-modify-write to change an output and a GPIO module which has separate
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* set/clr registers to directly change outputs with a single write access.
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*/
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#if defined(CONFIG_M528x)
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/*
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* The 528x also has GPIOs in other modules (GPT, QADC) which use
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* read-modify-write as well as those controlled by the EPORT and GPIO modules.
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*/
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#define MCFGPIO_SCR_START 40
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#elif defined(CONFIGM5441x)
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/* The m5441x EPORT doesn't have its own GPIO port, uses PORT C */
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#define MCFGPIO_SCR_START 0
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#else
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#define MCFGPIO_SCR_START 8
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#endif
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#define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
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mcfgpio_port(gpio - MCFGPIO_SCR_START))
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#define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
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mcfgpio_port(gpio - MCFGPIO_SCR_START))
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#else
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#define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
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/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
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#define MCFGPIO_SETR_PORT(gpio) 0
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#define MCFGPIO_CLRR_PORT(gpio) 0
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#endif
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/*
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* Coldfire specific helper functions
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*/
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/* return the port pin data register for a gpio */
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static inline u32 __mcfgpio_ppdr(unsigned gpio)
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{
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#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
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defined(CONFIG_M5307) || defined(CONFIG_M5407)
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return MCFSIM_PADAT;
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#elif defined(CONFIG_M5272)
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if (gpio < 16)
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return MCFSIM_PADAT;
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else if (gpio < 32)
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return MCFSIM_PBDAT;
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else
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return MCFSIM_PCDAT;
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#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
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if (gpio < 32)
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return MCFSIM2_GPIOREAD;
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else
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return MCFSIM2_GPIO1READ;
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#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
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defined(CONFIG_M5441x)
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#if !defined(CONFIG_M5441x)
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if (gpio < 8)
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return MCFEPORT_EPPDR;
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#if defined(CONFIG_M528x)
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else if (gpio < 16)
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return MCFGPTA_GPTPORT;
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else if (gpio < 24)
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return MCFGPTB_GPTPORT;
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else if (gpio < 32)
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return MCFQADC_PORTQA;
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else if (gpio < 40)
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return MCFQADC_PORTQB;
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#endif /* defined(CONFIG_M528x) */
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else
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#endif /* !defined(CONFIG_M5441x) */
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return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
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#else
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return 0;
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#endif
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}
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/* return the port output data register for a gpio */
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static inline u32 __mcfgpio_podr(unsigned gpio)
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{
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#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
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defined(CONFIG_M5307) || defined(CONFIG_M5407)
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return MCFSIM_PADAT;
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#elif defined(CONFIG_M5272)
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if (gpio < 16)
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return MCFSIM_PADAT;
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else if (gpio < 32)
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return MCFSIM_PBDAT;
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else
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return MCFSIM_PCDAT;
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#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
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if (gpio < 32)
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return MCFSIM2_GPIOWRITE;
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else
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return MCFSIM2_GPIO1WRITE;
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#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
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defined(CONFIG_M5441x)
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#if !defined(CONFIG_M5441x)
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if (gpio < 8)
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return MCFEPORT_EPDR;
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#if defined(CONFIG_M528x)
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else if (gpio < 16)
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return MCFGPTA_GPTPORT;
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else if (gpio < 24)
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return MCFGPTB_GPTPORT;
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else if (gpio < 32)
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return MCFQADC_PORTQA;
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else if (gpio < 40)
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return MCFQADC_PORTQB;
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#endif /* defined(CONFIG_M528x) */
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else
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#endif /* !defined(CONFIG_M5441x) */
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return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
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#else
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return 0;
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#endif
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}
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/* return the port direction data register for a gpio */
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static inline u32 __mcfgpio_pddr(unsigned gpio)
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{
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#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
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defined(CONFIG_M5307) || defined(CONFIG_M5407)
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return MCFSIM_PADDR;
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#elif defined(CONFIG_M5272)
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if (gpio < 16)
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return MCFSIM_PADDR;
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else if (gpio < 32)
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return MCFSIM_PBDDR;
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else
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return MCFSIM_PCDDR;
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#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
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if (gpio < 32)
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return MCFSIM2_GPIOENABLE;
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else
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return MCFSIM2_GPIO1ENABLE;
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#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
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defined(CONFIG_M5441x)
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#if !defined(CONFIG_M5441x)
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if (gpio < 8)
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return MCFEPORT_EPDDR;
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#if defined(CONFIG_M528x)
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else if (gpio < 16)
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return MCFGPTA_GPTDDR;
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else if (gpio < 24)
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return MCFGPTB_GPTDDR;
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else if (gpio < 32)
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return MCFQADC_DDRQA;
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else if (gpio < 40)
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return MCFQADC_DDRQB;
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#endif /* defined(CONFIG_M528x) */
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else
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#endif /* !defined(CONFIG_M5441x) */
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return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
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#else
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return 0;
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#endif
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}
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#endif /* mcfgpio_h */
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