101 lines
2.0 KiB
Plaintext
101 lines
2.0 KiB
Plaintext
|
// SPDX-License-Identifier: GPL-2.0
|
||
|
|
/dts-v1/;
|
||
|
|
/ {
|
||
|
|
compatible = "gnu,gdbsim";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
interrupt-parent = <&h8intc>;
|
||
|
|
|
||
|
|
chosen {
|
||
|
|
bootargs = "earlyprintk=h8300-sim";
|
||
|
|
stdout-path = <&sci0>;
|
||
|
|
};
|
||
|
|
aliases {
|
||
|
|
serial0 = &sci0;
|
||
|
|
serial1 = &sci1;
|
||
|
|
};
|
||
|
|
|
||
|
|
xclk: oscillator {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
clock-frequency = <33333333>;
|
||
|
|
clock-output-names = "xtal";
|
||
|
|
};
|
||
|
|
pllclk: pllclk {
|
||
|
|
compatible = "renesas,h8s2678-pll-clock";
|
||
|
|
clocks = <&xclk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
reg = <0xfee03b 2>, <0xfee045 2>;
|
||
|
|
};
|
||
|
|
core_clk: core_clk {
|
||
|
|
compatible = "renesas,h8300-div-clock";
|
||
|
|
clocks = <&pllclk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
reg = <0xfee03b 2>;
|
||
|
|
renesas,width = <3>;
|
||
|
|
};
|
||
|
|
fclk: fclk {
|
||
|
|
compatible = "fixed-factor-clock";
|
||
|
|
clocks = <&core_clk>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-div = <1>;
|
||
|
|
clock-mult = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
memory@400000 {
|
||
|
|
device_type = "memory";
|
||
|
|
reg = <0x400000 0x800000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cpus {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
cpu@0 {
|
||
|
|
compatible = "renesas,h8300";
|
||
|
|
clock-frequency = <33333333>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
h8intc: interrupt-controller@fffe00 {
|
||
|
|
compatible = "renesas,h8s-intc", "renesas,h8300-intc";
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
reg = <0xfffe00 24>;
|
||
|
|
};
|
||
|
|
|
||
|
|
bsc: memory-controller@fffec0 {
|
||
|
|
compatible = "renesas,h8s-bsc", "renesas,h8300-bsc";
|
||
|
|
reg = <0xfffec0 24>;
|
||
|
|
};
|
||
|
|
|
||
|
|
tpu: timer@ffffe0 {
|
||
|
|
compatible = "renesas,tpu";
|
||
|
|
reg = <0xffffe0 16>, <0xfffff0 12>;
|
||
|
|
clocks = <&fclk>;
|
||
|
|
clock-names = "fck";
|
||
|
|
};
|
||
|
|
|
||
|
|
timer8: timer@ffffb0 {
|
||
|
|
compatible = "renesas,8bit-timer";
|
||
|
|
reg = <0xffffb0 10>;
|
||
|
|
interrupts = <72 0>;
|
||
|
|
clocks = <&fclk>;
|
||
|
|
clock-names = "fck";
|
||
|
|
};
|
||
|
|
|
||
|
|
sci0: serial@ffff78 {
|
||
|
|
compatible = "renesas,sci";
|
||
|
|
reg = <0xffff78 8>;
|
||
|
|
interrupts = <88 0>, <89 0>, <90 0>, <91 0>;
|
||
|
|
clocks = <&fclk>;
|
||
|
|
clock-names = "fck";
|
||
|
|
};
|
||
|
|
sci1: serial@ffff80 {
|
||
|
|
compatible = "renesas,sci";
|
||
|
|
reg = <0xffff80 8>;
|
||
|
|
interrupts = <92 0>, <93 0>, <94 0>, <95 0>;
|
||
|
|
clocks = <&fclk>;
|
||
|
|
clock-names = "fck";
|
||
|
|
};
|
||
|
|
};
|