400 lines
9.3 KiB
C
400 lines
9.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* OMAP2xxx CM module functions
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*
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* Copyright (C) 2009 Nokia Corporation
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* Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
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* Paul Walmsley
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* Rajendra Nayak <rnayak@ti.com>
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include "prm2xxx.h"
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#include "cm.h"
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#include "cm2xxx.h"
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#include "cm-regbits-24xx.h"
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#include "clockdomain.h"
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/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
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#define DPLL_AUTOIDLE_DISABLE 0x0
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#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
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/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
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#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0
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#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
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/* CM_IDLEST_PLL bit value offset for APLLs (OMAP2xxx only) */
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#define EN_APLL_LOCKED 3
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static const u8 omap2xxx_cm_idlest_offs[] = {
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CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
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};
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/*
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*
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*/
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static void _write_clktrctrl(u8 c, s16 module, u32 mask)
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{
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u32 v;
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v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
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v &= ~mask;
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v |= c << __ffs(mask);
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omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
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}
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static bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
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{
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u32 v;
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v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
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v &= mask;
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v >>= __ffs(mask);
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return (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
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}
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static void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
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{
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_write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
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}
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static void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
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{
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_write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
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}
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/*
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* DPLL autoidle control
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*/
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static void _omap2xxx_set_dpll_autoidle(u8 m)
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{
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u32 v;
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v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
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v &= ~OMAP24XX_AUTO_DPLL_MASK;
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v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
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omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
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}
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void omap2xxx_cm_set_dpll_disable_autoidle(void)
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{
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_omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
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}
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void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
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{
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_omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
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}
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/*
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* APLL control
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*/
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static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
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{
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u32 v;
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v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
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v &= ~mask;
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v |= m << __ffs(mask);
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omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
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}
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void omap2xxx_cm_set_apll54_disable_autoidle(void)
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{
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_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
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OMAP24XX_AUTO_54M_MASK);
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}
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void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
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{
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_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
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OMAP24XX_AUTO_54M_MASK);
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}
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void omap2xxx_cm_set_apll96_disable_autoidle(void)
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{
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_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
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OMAP24XX_AUTO_96M_MASK);
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}
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void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
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{
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_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
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OMAP24XX_AUTO_96M_MASK);
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}
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/* Enable an APLL if off */
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static int _omap2xxx_apll_enable(u8 enable_bit, u8 status_bit)
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{
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u32 v, m;
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m = EN_APLL_LOCKED << enable_bit;
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v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
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if (v & m)
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return 0; /* apll already enabled */
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v |= m;
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omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN);
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omap2xxx_cm_wait_module_ready(0, PLL_MOD, 1, status_bit);
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/*
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* REVISIT: Should we return an error code if
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* omap2xxx_cm_wait_module_ready() fails?
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*/
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return 0;
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}
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/* Stop APLL */
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static void _omap2xxx_apll_disable(u8 enable_bit)
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{
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u32 v;
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v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
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v &= ~(EN_APLL_LOCKED << enable_bit);
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omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN);
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}
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/* Enable an APLL if off */
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int omap2xxx_cm_apll54_enable(void)
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{
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return _omap2xxx_apll_enable(OMAP24XX_EN_54M_PLL_SHIFT,
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OMAP24XX_ST_54M_APLL_SHIFT);
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}
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/* Enable an APLL if off */
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int omap2xxx_cm_apll96_enable(void)
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{
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return _omap2xxx_apll_enable(OMAP24XX_EN_96M_PLL_SHIFT,
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OMAP24XX_ST_96M_APLL_SHIFT);
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}
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/* Stop APLL */
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void omap2xxx_cm_apll54_disable(void)
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{
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_omap2xxx_apll_disable(OMAP24XX_EN_54M_PLL_SHIFT);
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}
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/* Stop APLL */
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void omap2xxx_cm_apll96_disable(void)
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{
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_omap2xxx_apll_disable(OMAP24XX_EN_96M_PLL_SHIFT);
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}
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/**
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* omap2xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
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* @idlest_reg: CM_IDLEST* virtual address
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* @prcm_inst: pointer to an s16 to return the PRCM instance offset
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* @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
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*
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* XXX This function is only needed until absolute register addresses are
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* removed from the OMAP struct clk records.
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*/
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static int omap2xxx_cm_split_idlest_reg(struct clk_omap_reg *idlest_reg,
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s16 *prcm_inst,
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u8 *idlest_reg_id)
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{
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unsigned long offs;
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u8 idlest_offs;
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int i;
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idlest_offs = idlest_reg->offset & 0xff;
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for (i = 0; i < ARRAY_SIZE(omap2xxx_cm_idlest_offs); i++) {
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if (idlest_offs == omap2xxx_cm_idlest_offs[i]) {
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*idlest_reg_id = i + 1;
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break;
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}
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}
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if (i == ARRAY_SIZE(omap2xxx_cm_idlest_offs))
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return -EINVAL;
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offs = idlest_reg->offset;
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offs &= 0xff00;
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*prcm_inst = offs;
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return 0;
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}
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/*
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*
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*/
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/**
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* omap2xxx_cm_wait_module_ready - wait for a module to leave idle or standby
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* @part: PRCM partition, ignored for OMAP2
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* @prcm_mod: PRCM module offset
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* @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
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* @idlest_shift: shift of the bit in the CM_IDLEST* register to check
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*
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* Wait for the PRCM to indicate that the module identified by
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* (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon
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* success or -EBUSY if the module doesn't enable in time.
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*/
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int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
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u8 idlest_shift)
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{
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int ena = 0, i = 0;
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u8 cm_idlest_reg;
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u32 mask;
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if (!idlest_id || (idlest_id > ARRAY_SIZE(omap2xxx_cm_idlest_offs)))
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return -EINVAL;
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cm_idlest_reg = omap2xxx_cm_idlest_offs[idlest_id - 1];
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mask = 1 << idlest_shift;
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ena = mask;
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omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
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mask) == ena), MAX_MODULE_READY_TIME, i);
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return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
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}
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/* Clockdomain low-level functions */
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static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm)
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{
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omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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}
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static void omap2xxx_clkdm_deny_idle(struct clockdomain *clkdm)
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{
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omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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}
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static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
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{
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bool hwsup = false;
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if (!clkdm->clktrctrl_mask)
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return 0;
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hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
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omap2xxx_clkdm_wakeup(clkdm);
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return 0;
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}
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static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm)
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{
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bool hwsup = false;
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if (!clkdm->clktrctrl_mask)
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return 0;
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hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
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omap2xxx_clkdm_sleep(clkdm);
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return 0;
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}
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struct clkdm_ops omap2_clkdm_operations = {
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.clkdm_add_wkdep = omap2_clkdm_add_wkdep,
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.clkdm_del_wkdep = omap2_clkdm_del_wkdep,
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.clkdm_read_wkdep = omap2_clkdm_read_wkdep,
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.clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
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.clkdm_sleep = omap2xxx_clkdm_sleep,
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.clkdm_wakeup = omap2xxx_clkdm_wakeup,
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.clkdm_allow_idle = omap2xxx_clkdm_allow_idle,
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.clkdm_deny_idle = omap2xxx_clkdm_deny_idle,
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.clkdm_clk_enable = omap2xxx_clkdm_clk_enable,
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.clkdm_clk_disable = omap2xxx_clkdm_clk_disable,
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};
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int omap2xxx_cm_fclks_active(void)
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{
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u32 f1, f2;
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f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
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f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
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return (f1 | f2) ? 1 : 0;
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}
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int omap2xxx_cm_mpu_retention_allowed(void)
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{
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u32 l;
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/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
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l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
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if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
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OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
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OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
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return 0;
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/* Check for UART3. */
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l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
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if (l & OMAP24XX_EN_UART3_MASK)
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return 0;
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return 1;
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}
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u32 omap2xxx_cm_get_core_clk_src(void)
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{
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u32 v;
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v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
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v &= OMAP24XX_CORE_CLK_SRC_MASK;
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return v;
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}
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u32 omap2xxx_cm_get_core_pll_config(void)
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{
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return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
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}
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void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
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{
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u32 tmp;
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omap2_cm_write_mod_reg(mpu, MPU_MOD, CM_CLKSEL);
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omap2_cm_write_mod_reg(dsp, OMAP24XX_DSP_MOD, CM_CLKSEL);
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omap2_cm_write_mod_reg(gfx, GFX_MOD, CM_CLKSEL);
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tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) &
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OMAP24XX_CLKSEL_DSS2_MASK;
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omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1);
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if (mdm)
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omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL);
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}
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/*
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*
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*/
|
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static const struct cm_ll_data omap2xxx_cm_ll_data = {
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.split_idlest_reg = &omap2xxx_cm_split_idlest_reg,
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.wait_module_ready = &omap2xxx_cm_wait_module_ready,
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};
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|
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int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data)
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{
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return cm_register(&omap2xxx_cm_ll_data);
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}
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static void __exit omap2xxx_cm_exit(void)
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{
|
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cm_unregister(&omap2xxx_cm_ll_data);
|
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}
|
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__exitcall(omap2xxx_cm_exit);
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