164 lines
6.1 KiB
ReStructuredText
164 lines
6.1 KiB
ReStructuredText
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.. SPDX-License-Identifier: GPL-2.0
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======================
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Generic vcpu interface
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======================
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The virtual cpu "device" also accepts the ioctls KVM_SET_DEVICE_ATTR,
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KVM_GET_DEVICE_ATTR, and KVM_HAS_DEVICE_ATTR. The interface uses the same struct
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kvm_device_attr as other devices, but targets VCPU-wide settings and controls.
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The groups and attributes per virtual cpu, if any, are architecture specific.
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1. GROUP: KVM_ARM_VCPU_PMU_V3_CTRL
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==================================
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:Architectures: ARM64
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1.1. ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_IRQ
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---------------------------------------
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:Parameters: in kvm_device_attr.addr the address for PMU overflow interrupt is a
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pointer to an int
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Returns:
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======= ========================================================
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-EBUSY The PMU overflow interrupt is already set
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-EFAULT Error reading interrupt number
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-ENXIO PMUv3 not supported or the overflow interrupt not set
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when attempting to get it
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-ENODEV KVM_ARM_VCPU_PMU_V3 feature missing from VCPU
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-EINVAL Invalid PMU overflow interrupt number supplied or
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trying to set the IRQ number without using an in-kernel
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irqchip.
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======= ========================================================
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A value describing the PMUv3 (Performance Monitor Unit v3) overflow interrupt
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number for this vcpu. This interrupt could be a PPI or SPI, but the interrupt
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type must be same for each vcpu. As a PPI, the interrupt number is the same for
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all vcpus, while as an SPI it must be a separate number per vcpu.
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1.2 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_INIT
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---------------------------------------
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:Parameters: no additional parameter in kvm_device_attr.addr
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Returns:
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======= ======================================================
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-EEXIST Interrupt number already used
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-ENODEV PMUv3 not supported or GIC not initialized
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-ENXIO PMUv3 not supported, missing VCPU feature or interrupt
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number not set
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-EBUSY PMUv3 already initialized
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======= ======================================================
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Request the initialization of the PMUv3. If using the PMUv3 with an in-kernel
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virtual GIC implementation, this must be done after initializing the in-kernel
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irqchip.
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1.3 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_FILTER
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-----------------------------------------
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:Parameters: in kvm_device_attr.addr the address for a PMU event filter is a
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pointer to a struct kvm_pmu_event_filter
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:Returns:
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======= ======================================================
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-ENODEV PMUv3 not supported or GIC not initialized
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-ENXIO PMUv3 not properly configured or in-kernel irqchip not
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configured as required prior to calling this attribute
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-EBUSY PMUv3 already initialized
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-EINVAL Invalid filter range
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======= ======================================================
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Request the installation of a PMU event filter described as follows::
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struct kvm_pmu_event_filter {
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__u16 base_event;
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__u16 nevents;
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#define KVM_PMU_EVENT_ALLOW 0
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#define KVM_PMU_EVENT_DENY 1
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__u8 action;
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__u8 pad[3];
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};
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A filter range is defined as the range [@base_event, @base_event + @nevents),
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together with an @action (KVM_PMU_EVENT_ALLOW or KVM_PMU_EVENT_DENY). The
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first registered range defines the global policy (global ALLOW if the first
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@action is DENY, global DENY if the first @action is ALLOW). Multiple ranges
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can be programmed, and must fit within the event space defined by the PMU
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architecture (10 bits on ARMv8.0, 16 bits from ARMv8.1 onwards).
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Note: "Cancelling" a filter by registering the opposite action for the same
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range doesn't change the default action. For example, installing an ALLOW
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filter for event range [0:10) as the first filter and then applying a DENY
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action for the same range will leave the whole range as disabled.
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Restrictions: Event 0 (SW_INCR) is never filtered, as it doesn't count a
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hardware event. Filtering event 0x1E (CHAIN) has no effect either, as it
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isn't strictly speaking an event. Filtering the cycle counter is possible
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using event 0x11 (CPU_CYCLES).
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2. GROUP: KVM_ARM_VCPU_TIMER_CTRL
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=================================
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:Architectures: ARM, ARM64
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2.1. ATTRIBUTES: KVM_ARM_VCPU_TIMER_IRQ_VTIMER, KVM_ARM_VCPU_TIMER_IRQ_PTIMER
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-----------------------------------------------------------------------------
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:Parameters: in kvm_device_attr.addr the address for the timer interrupt is a
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pointer to an int
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Returns:
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======= =================================
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-EINVAL Invalid timer interrupt number
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-EBUSY One or more VCPUs has already run
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======= =================================
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A value describing the architected timer interrupt number when connected to an
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in-kernel virtual GIC. These must be a PPI (16 <= intid < 32). Setting the
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attribute overrides the default values (see below).
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============================= ==========================================
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KVM_ARM_VCPU_TIMER_IRQ_VTIMER The EL1 virtual timer intid (default: 27)
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KVM_ARM_VCPU_TIMER_IRQ_PTIMER The EL1 physical timer intid (default: 30)
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============================= ==========================================
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Setting the same PPI for different timers will prevent the VCPUs from running.
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Setting the interrupt number on a VCPU configures all VCPUs created at that
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time to use the number provided for a given timer, overwriting any previously
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configured values on other VCPUs. Userspace should configure the interrupt
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numbers on at least one VCPU after creating all VCPUs and before running any
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VCPUs.
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3. GROUP: KVM_ARM_VCPU_PVTIME_CTRL
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==================================
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:Architectures: ARM64
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3.1 ATTRIBUTE: KVM_ARM_VCPU_PVTIME_IPA
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--------------------------------------
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:Parameters: 64-bit base address
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Returns:
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======= ======================================
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-ENXIO Stolen time not implemented
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-EEXIST Base address already set for this VCPU
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-EINVAL Base address not 64 byte aligned
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======= ======================================
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Specifies the base address of the stolen time structure for this VCPU. The
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base address must be 64 byte aligned and exist within a valid guest memory
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region. See Documentation/virt/kvm/arm/pvtime.rst for more information
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including the layout of the stolen time structure.
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