39 lines
1.1 KiB
Plaintext
39 lines
1.1 KiB
Plaintext
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* Freescale MPIC timers
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Required properties:
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- compatible: "fsl,mpic-global-timer"
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- reg : Contains two regions. The first is the main timer register bank
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(GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control
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register (TCRx) for the group.
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- fsl,available-ranges: use <start count> style section to define which
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timer interrupts can be used. This property is optional; without this,
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all timers within the group can be used.
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- interrupts: one interrupt per timer in the group, in order, starting
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with timer zero. If timer-available-ranges is present, only the
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interrupts that correspond to available timers shall be present.
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Example:
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/* Note that this requires #interrupt-cells to be 4 */
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timer0: timer@41100 {
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compatible = "fsl,mpic-global-timer";
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reg = <0x41100 0x100 0x41300 4>;
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/* Another AMP partition is using timers 0 and 1 */
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fsl,available-ranges = <2 2>;
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interrupts = <2 0 3 0
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3 0 3 0>;
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};
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timer1: timer@42100 {
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compatible = "fsl,mpic-global-timer";
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reg = <0x42100 0x100 0x42300 4>;
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interrupts = <4 0 3 0
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5 0 3 0
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6 0 3 0
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7 0 3 0>;
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};
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