68 lines
2.0 KiB
Plaintext
68 lines
2.0 KiB
Plaintext
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* Device tree bindings for Texas Instruments keystone reset
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This node is intended to allow SoC reset in case of software reset
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of selected watchdogs.
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The Keystone SoCs can contain up to 4 watchdog timers to reset
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SoC. Each watchdog timer event input is connected to the Reset Mux
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block. The Reset Mux block can be configured to cause reset or not.
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Additionally soft or hard reset can be configured.
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Required properties:
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- compatible: ti,keystone-reset
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- ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
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access pll controller registers and the offset to use
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reset control registers.
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- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
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access device state control registers and the offset
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in order to use mux block registers for all watchdogs.
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Optional properties:
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- ti,soft-reset: Boolean option indicating soft reset.
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By default hard reset is used.
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- ti,wdt-list: WDT list that can cause SoC reset. It's not related
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to WDT driver, it's just needed to enable a SoC related
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reset that's triggered by one of WDTs. The list is
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in format: <0>, <2>; It can be in random order and
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begins from 0 to 3, as keystone can contain up to 4 SoC
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reset watchdogs and can be in random order.
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Example 1:
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Setup keystone reset so that in case software reset or
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WDT0 is triggered it issues hard reset for SoC.
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pllctrl: pll-controller@2310000 {
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compatible = "ti,keystone-pllctrl", "syscon";
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reg = <0x02310000 0x200>;
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};
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devctrl: device-state-control@2620000 {
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compatible = "ti,keystone-devctrl", "syscon";
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reg = <0x02620000 0x1000>;
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};
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rstctrl: reset-controller {
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compatible = "ti,keystone-reset";
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ti,syscon-pll = <&pllctrl 0xe4>;
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ti,syscon-dev = <&devctrl 0x328>;
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ti,wdt-list = <0>;
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};
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Example 2:
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Setup keystone reset so that in case of software reset or
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WDT0 or WDT2 is triggered it issues soft reset for SoC.
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rstctrl: reset-controller {
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compatible = "ti,keystone-reset";
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ti,syscon-pll = <&pllctrl 0xe4>;
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ti,syscon-dev = <&devctrl 0x328>;
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ti,wdt-list = <0>, <2>;
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ti,soft-reset;
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};
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