191 lines
6.7 KiB
YAML
191 lines
6.7 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/A1 combined Pin and GPIO controller
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maintainers:
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- Jacopo Mondi <jacopo+renesas@jmondi.org>
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description:
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The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO
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controller, named "Ports" in the hardware reference manual.
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Pin multiplexing and GPIO configuration is performed on a per-pin basis
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writing configuration values to per-port register sets.
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Each "port" features up to 16 pins, each of them configurable for GPIO
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function (port mode) or in alternate function mode.
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Up to 8 different alternate function modes exist for each single pin.
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properties:
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compatible:
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oneOf:
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- const: renesas,r7s72100-ports # RZ/A1H
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- items:
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- const: renesas,r7s72101-ports # RZ/A1M
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- const: renesas,r7s72100-ports # fallback
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- const: renesas,r7s72102-ports # RZ/A1L
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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patternProperties:
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"^gpio-[0-9]*$":
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type: object
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description:
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Each port of the r7s72100 pin controller hardware is itself a GPIO
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controller.
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Different SoCs have different numbers of available pins per port, but
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generally speaking, each of them can be configured in GPIO ("port") mode
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on this hardware.
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Describe GPIO controllers using sub-nodes with the following properties.
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properties:
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gpio-controller: true
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'#gpio-cells':
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const: 2
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gpio-ranges:
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maxItems: 1
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required:
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- gpio-controller
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- '#gpio-cells'
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- gpio-ranges
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additionalProperties:
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anyOf:
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- type: object
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allOf:
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- $ref: pincfg-node.yaml#
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- $ref: pinmux-node.yaml#
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description:
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A pin multiplexing sub-node describes how to configure a set of (or a
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single) pin in some desired alternate function mode.
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A single sub-node may define several pin configurations.
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A few alternate function require special pin configuration flags to be
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supplied along with the alternate function configuration number.
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The hardware reference manual specifies when a pin function requires
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"software IO driven" mode to be specified. To do so use the generic
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properties from the <include/linux/pinctrl/pinconf_generic.h> header
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file to instruct the pin controller to perform the desired pin
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configuration operation.
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The hardware reference manual specifies when a pin has to be configured
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to work in bi-directional mode and when the IO direction has to be
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specified by software. Bi-directional pins must be managed by the pin
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controller driver internally, while software driven IO direction has to
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be explicitly selected when multiple options are available.
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properties:
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pinmux:
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description: |
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Integer array representing pin number and pin multiplexing
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configuration.
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When a pin has to be configured in alternate function mode, use
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this property to identify the pin by its global index, and provide
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its alternate function configuration number along with it.
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When multiple pins are required to be configured as part of the
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same alternate function they shall be specified as members of the
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same argument list of a single "pinmux" property.
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Helper macros to ease assembling the pin index from its position
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(port where it sits on and pin number) and alternate function
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identifier are provided by the pin controller header file at:
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<include/dt-bindings/pinctrl/r7s72100-pinctrl.h>
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Integers values in "pinmux" argument list are assembled as:
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((PORT * 16 + PIN) | MUX_FUNC << 16)
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phandle: true
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input-enable: true
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output-enable: true
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required:
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- pinmux
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additionalProperties: false
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- type: object
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properties:
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phandle: true
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additionalProperties:
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$ref: "#/additionalProperties/anyOf/0"
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examples:
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- |
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#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
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pinctrl: pinctrl@fcfe3000 {
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compatible = "renesas,r7s72100-ports";
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reg = <0xfcfe3000 0x4230>;
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/*
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* A GPIO controller node, controlling 16 pins indexed from 0.
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* The GPIO controller base in the global pin indexing space is pin
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* 48, thus pins [0 - 15] on this controller map to pins [48 - 63]
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* in the global pin indexing space.
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*/
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port3: gpio-3 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 48 16>;
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};
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/*
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* A serial communication interface with a TX output pin and an RX
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* input pin.
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* Pin #0 on port #3 is configured as alternate function #6.
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* Pin #2 on port #3 is configured as alternate function #4.
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*/
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scif2_pins: serial2 {
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pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
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};
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/*
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* I2c master: both SDA and SCL pins need bi-directional operations
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* Pin #4 on port #1 is configured as alternate function #1.
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* Pin #5 on port #1 is configured as alternate function #1.
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* Both need to work in bi-directional mode, the driver must manage
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* this internally.
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*/
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i2c2_pins: i2c2 {
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pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
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};
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/*
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* Multi-function timer input and output compare pins.
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*/
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tioc0_pins: tioc0 {
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/*
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* Configure TIOC0A as software driven input
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* Pin #0 on port #4 is configured as alternate function #2
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* with IO direction specified by software as input.
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*/
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tioc0_input_pins {
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pinmux = <RZA1_PINMUX(4, 0, 2)>;
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input-enable;
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};
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/*
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* Configure TIOC0B as software driven output
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* Pin #1 on port #4 is configured as alternate function #1
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* with IO direction specified by software as output.
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*/
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tioc0_output_pins {
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pinmux = <RZA1_PINMUX(4, 1, 1)>;
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output-enable;
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};
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};
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};
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