73 lines
2.4 KiB
Plaintext
73 lines
2.4 KiB
Plaintext
|
* Mobiveil AXI PCIe Root Port Bridge DT description
|
||
|
|
|
||
|
|
Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP
|
||
|
|
has up to 8 outbound and inbound windows for the address translation.
|
||
|
|
|
||
|
|
Required properties:
|
||
|
|
- #address-cells: Address representation for root ports, set to <3>
|
||
|
|
- #size-cells: Size representation for root ports, set to <2>
|
||
|
|
- #interrupt-cells: specifies the number of cells needed to encode an
|
||
|
|
interrupt source. The value must be 1.
|
||
|
|
- compatible: Should contain "mbvl,gpex40-pcie"
|
||
|
|
- reg: Should contain PCIe registers location and length
|
||
|
|
Mandatory:
|
||
|
|
"config_axi_slave": PCIe controller registers
|
||
|
|
"csr_axi_slave" : Bridge config registers
|
||
|
|
Optional:
|
||
|
|
"gpio_slave" : GPIO registers to control slot power
|
||
|
|
"apb_csr" : MSI registers
|
||
|
|
|
||
|
|
- device_type: must be "pci"
|
||
|
|
- apio-wins : number of requested apio outbound windows
|
||
|
|
default 2 outbound windows are configured -
|
||
|
|
1. Config window
|
||
|
|
2. Memory window
|
||
|
|
- ppio-wins : number of requested ppio inbound windows
|
||
|
|
default 1 inbound memory window is configured.
|
||
|
|
- bus-range: PCI bus numbers covered
|
||
|
|
- interrupt-controller: identifies the node as an interrupt controller
|
||
|
|
- #interrupt-cells: specifies the number of cells needed to encode an
|
||
|
|
interrupt source. The value must be 1.
|
||
|
|
- interrupts: The interrupt line of the PCIe controller
|
||
|
|
last cell of this field is set to 4 to
|
||
|
|
denote it as IRQ_TYPE_LEVEL_HIGH type interrupt.
|
||
|
|
- interrupt-map-mask,
|
||
|
|
interrupt-map: standard PCI properties to define the mapping of the
|
||
|
|
PCI interface to interrupt numbers.
|
||
|
|
- ranges: ranges for the PCI memory regions (I/O space region is not
|
||
|
|
supported by hardware)
|
||
|
|
Please refer to the standard PCI bus binding document for a more
|
||
|
|
detailed explanation
|
||
|
|
|
||
|
|
|
||
|
|
Example:
|
||
|
|
++++++++
|
||
|
|
pcie0: pcie@a0000000 {
|
||
|
|
#address-cells = <3>;
|
||
|
|
#size-cells = <2>;
|
||
|
|
compatible = "mbvl,gpex40-pcie";
|
||
|
|
reg = <0xa0000000 0x00001000>,
|
||
|
|
<0xb0000000 0x00010000>,
|
||
|
|
<0xff000000 0x00200000>,
|
||
|
|
<0xb0010000 0x00001000>;
|
||
|
|
reg-names = "config_axi_slave",
|
||
|
|
"csr_axi_slave",
|
||
|
|
"gpio_slave",
|
||
|
|
"apb_csr";
|
||
|
|
device_type = "pci";
|
||
|
|
apio-wins = <2>;
|
||
|
|
ppio-wins = <1>;
|
||
|
|
bus-range = <0x00000000 0x000000ff>;
|
||
|
|
interrupt-controller;
|
||
|
|
interrupt-parent = <&gic>;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
interrupts = < 0 89 4 >;
|
||
|
|
interrupt-map-mask = <0 0 0 7>;
|
||
|
|
interrupt-map = <0 0 0 0 &pci_express 0>,
|
||
|
|
<0 0 0 1 &pci_express 1>,
|
||
|
|
<0 0 0 2 &pci_express 2>,
|
||
|
|
<0 0 0 3 &pci_express 3>;
|
||
|
|
ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;
|
||
|
|
|
||
|
|
};
|