51 lines
1.8 KiB
Plaintext
51 lines
1.8 KiB
Plaintext
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* Altera PCIe controller
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Required properties:
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- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
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- reg: a list of physical base address and length for TXS and CRA.
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For "altr,pcie-root-port-2.0", additional HIP base address and length.
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- reg-names: must include the following entries:
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"Txs": TX slave port region
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"Cra": Control register access region
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"Hip": Hard IP region (if "altr,pcie-root-port-2.0")
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- interrupts: specifies the interrupt source of the parent interrupt
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controller. The format of the interrupt specifier depends
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on the parent interrupt controller.
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- device_type: must be "pci"
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- #interrupt-cells: set to <1>
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- ranges: describes the translation of addresses for root ports and
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standard PCI regions.
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- interrupt-map-mask and interrupt-map: standard PCI properties to define the
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mapping of the PCIe interface to interrupt numbers.
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Optional properties:
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- msi-parent: Link to the hardware entity that serves as the MSI controller
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for this PCIe controller.
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- bus-range: PCI bus numbers covered
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Example
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pcie_0: pcie@c00000000 {
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compatible = "altr,pcie-root-port-1.0";
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reg = <0xc0000000 0x20000000>,
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<0xff220000 0x00004000>;
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reg-names = "Txs", "Cra";
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interrupt-parent = <&hps_0_arm_gic_0>;
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interrupts = <0 40 4>;
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interrupt-controller;
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#interrupt-cells = <1>;
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bus-range = <0x0 0xFF>;
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device_type = "pci";
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msi-parent = <&msi_to_gic_gen_0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_0 1>,
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<0 0 0 2 &pcie_0 2>,
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<0 0 0 3 &pcie_0 3>,
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<0 0 0 4 &pcie_0 4>;
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ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
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0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
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};
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