101 lines
2.6 KiB
Plaintext
101 lines
2.6 KiB
Plaintext
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Cadence MIPI-CSI2 RX controller
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===============================
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The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
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lanes in input, and 4 different pixel streams in output.
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Required properties:
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- compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
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- reg: base address and size of the memory mapped region
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- clocks: phandles to the clocks driving the controller
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- clock-names: must contain:
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* sys_clk: main clock
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* p_clk: register bank clock
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* pixel_if[0-3]_clk: pixel stream output clock, one for each stream
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implemented in hardware, between 0 and 3
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Optional properties:
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- phys: phandle to the external D-PHY, phy-names must be provided
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- phy-names: must contain "dphy", if the implementation uses an
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external D-PHY
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Required subnodes:
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- ports: A ports node with one port child node per device input and output
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port, in accordance with the video interface bindings defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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port nodes are numbered as follows:
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Port Description
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-----------------------------
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0 CSI-2 input
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1 Stream 0 output
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2 Stream 1 output
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3 Stream 2 output
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4 Stream 3 output
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The stream output port nodes are optional if they are not
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connected to anything at the hardware level or implemented
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in the design.Since there is only one endpoint per port,
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the endpoints are not numbered.
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Example:
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csi2rx: csi-bridge@0d060000 {
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compatible = "cdns,csi2rx";
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reg = <0x0d060000 0x1000>;
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clocks = <&byteclock>, <&byteclock>
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<&coreclock>, <&coreclock>,
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<&coreclock>, <&coreclock>;
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clock-names = "sys_clk", "p_clk",
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"pixel_if0_clk", "pixel_if1_clk",
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"pixel_if2_clk", "pixel_if3_clk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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csi2rx_in_sensor: endpoint {
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remote-endpoint = <&sensor_out_csi2rx>;
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clock-lanes = <0>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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reg = <1>;
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csi2rx_out_grabber0: endpoint {
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remote-endpoint = <&grabber0_in_csi2rx>;
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};
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};
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port@2 {
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reg = <2>;
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csi2rx_out_grabber1: endpoint {
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remote-endpoint = <&grabber1_in_csi2rx>;
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};
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};
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port@3 {
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reg = <3>;
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csi2rx_out_grabber2: endpoint {
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remote-endpoint = <&grabber2_in_csi2rx>;
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};
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};
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port@4 {
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reg = <4>;
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csi2rx_out_grabber3: endpoint {
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remote-endpoint = <&grabber3_in_csi2rx>;
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};
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};
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};
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};
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