88 lines
3.9 KiB
Plaintext
88 lines
3.9 KiB
Plaintext
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NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver.
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Required properties:
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- compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or
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"nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c".
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For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be
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"nvidia,<chip>-i2c", plus at least one of the above, where <chip> is
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tegra124, tegra132, or tegra210.
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Details of compatible are as follows:
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nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
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controller. This only support master mode of I2C communication. Register
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interface/offset and interrupts handling are different than generic I2C
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controller. Driver of DVC I2C controller is only compatible with
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"nvidia,tegra20-i2c-dvc".
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nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support
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master and slave mode of I2C communication. The i2c-tegra driver only
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support master mode of I2C communication. Driver of I2C controller is
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only compatible with "nvidia,tegra20-i2c".
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nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is
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very much similar to Tegra20 I2C controller with additional feature:
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Continue Transfer Support. This feature helps to implement M_NO_START
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as per I2C core API transfer flags. Driver of I2C controller is
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compatible with "nvidia,tegra30-i2c" to enable the continue transfer
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support. This is also compatible with "nvidia,tegra20-i2c" without
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continue transfer support.
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nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is
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very much similar to Tegra30 I2C controller with some hardware
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modification:
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- Tegra30/Tegra20 I2C controller has 2 clock source called div-clk and
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fast-clk. Tegra114 has only one clock source called as div-clk and
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hence clock mechanism is changed in I2C controller.
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- Tegra30/Tegra20 I2C controller has enabled per packet transfer by
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default and there is no way to disable it. Tegra114 has this
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interrupt disable by default and SW need to enable explicitly.
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Due to above changes, Tegra114 I2C driver makes incompatible with
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previous hardware driver. Hence, tegra114 I2C controller is compatible
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with "nvidia,tegra114-i2c".
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nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is on host1x bus
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and is part of VE power domain and typically used for camera use-cases.
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This VI I2C controller is mostly compatible with the programming model
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of the regular I2C controllers with a few exceptions. The I2C registers
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start at an offset of 0xc00 (instead of 0), registers are 16 bytes
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apart (rather than 4) and the controller does not support slave mode.
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- reg: Should contain I2C controller registers physical address and length.
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- interrupts: Should contain I2C controller interrupts.
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- address-cells: Address cells for I2C device address.
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- size-cells: Size of the I2C device address.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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Tegra20/Tegra30:
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- div-clk
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- fast-clk
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Tegra114:
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- div-clk
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Tegra210:
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- div-clk
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- slow (only for nvidia,tegra210-i2c-vi compatible node)
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- i2c
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- power-domains: Only for nvidia,tegra210-i2c-vi compatible node and must
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include venc powergate node as vi i2c is part of VE power domain.
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tegra210-i2c-vi:
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- pd_venc
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- dmas: Must contain an entry for each entry in clock-names.
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See ../dma/dma.txt for details.
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- dma-names: Must include the following entries:
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- rx
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- tx
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Example:
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i2c@7000c000 {
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000c000 0x100>;
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interrupts = <0 38 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 12>, <&tegra_car 124>;
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clock-names = "div-clk", "fast-clk";
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resets = <&tegra_car 12>;
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reset-names = "i2c";
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dmas = <&apbdma 16>, <&apbdma 16>;
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dma-names = "rx", "tx";
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};
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