182 lines
5.2 KiB
C
182 lines
5.2 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2017 Intel Corporation. All rights reserved.
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*
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* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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*/
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#ifndef __SOF_INTEL_SHIM_H
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#define __SOF_INTEL_SHIM_H
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/*
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* SHIM registers for BYT, BSW, CHT, BDW
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*/
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#define SHIM_CSR (SHIM_OFFSET + 0x00)
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#define SHIM_PISR (SHIM_OFFSET + 0x08)
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#define SHIM_PIMR (SHIM_OFFSET + 0x10)
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#define SHIM_ISRX (SHIM_OFFSET + 0x18)
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#define SHIM_ISRD (SHIM_OFFSET + 0x20)
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#define SHIM_IMRX (SHIM_OFFSET + 0x28)
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#define SHIM_IMRD (SHIM_OFFSET + 0x30)
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#define SHIM_IPCX (SHIM_OFFSET + 0x38)
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#define SHIM_IPCD (SHIM_OFFSET + 0x40)
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#define SHIM_ISRSC (SHIM_OFFSET + 0x48)
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#define SHIM_ISRLPESC (SHIM_OFFSET + 0x50)
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#define SHIM_IMRSC (SHIM_OFFSET + 0x58)
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#define SHIM_IMRLPESC (SHIM_OFFSET + 0x60)
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#define SHIM_IPCSC (SHIM_OFFSET + 0x68)
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#define SHIM_IPCLPESC (SHIM_OFFSET + 0x70)
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#define SHIM_CLKCTL (SHIM_OFFSET + 0x78)
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#define SHIM_CSR2 (SHIM_OFFSET + 0x80)
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#define SHIM_LTRC (SHIM_OFFSET + 0xE0)
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#define SHIM_HMDC (SHIM_OFFSET + 0xE8)
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#define SHIM_PWMCTRL 0x1000
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/*
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* SST SHIM register bits for BYT, BSW, CHT, BDW
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* Register bit naming and functionaility can differ between devices.
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*/
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/* CSR / CS */
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#define SHIM_CSR_RST BIT(1)
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#define SHIM_CSR_SBCS0 BIT(2)
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#define SHIM_CSR_SBCS1 BIT(3)
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#define SHIM_CSR_DCS(x) ((x) << 4)
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#define SHIM_CSR_DCS_MASK (0x7 << 4)
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#define SHIM_CSR_STALL BIT(10)
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#define SHIM_CSR_S0IOCS BIT(21)
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#define SHIM_CSR_S1IOCS BIT(23)
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#define SHIM_CSR_LPCS BIT(31)
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#define SHIM_CSR_24MHZ_LPCS \
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(SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1 | SHIM_CSR_LPCS)
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#define SHIM_CSR_24MHZ_NO_LPCS (SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1)
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#define SHIM_BYT_CSR_RST BIT(0)
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#define SHIM_BYT_CSR_VECTOR_SEL BIT(1)
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#define SHIM_BYT_CSR_STALL BIT(2)
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#define SHIM_BYT_CSR_PWAITMODE BIT(3)
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/* ISRX / ISC */
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#define SHIM_ISRX_BUSY BIT(1)
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#define SHIM_ISRX_DONE BIT(0)
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#define SHIM_BYT_ISRX_REQUEST BIT(1)
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/* ISRD / ISD */
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#define SHIM_ISRD_BUSY BIT(1)
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#define SHIM_ISRD_DONE BIT(0)
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/* IMRX / IMC */
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#define SHIM_IMRX_BUSY BIT(1)
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#define SHIM_IMRX_DONE BIT(0)
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#define SHIM_BYT_IMRX_REQUEST BIT(1)
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/* IMRD / IMD */
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#define SHIM_IMRD_DONE BIT(0)
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#define SHIM_IMRD_BUSY BIT(1)
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#define SHIM_IMRD_SSP0 BIT(16)
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#define SHIM_IMRD_DMAC0 BIT(21)
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#define SHIM_IMRD_DMAC1 BIT(22)
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#define SHIM_IMRD_DMAC (SHIM_IMRD_DMAC0 | SHIM_IMRD_DMAC1)
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/* IPCX / IPCC */
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#define SHIM_IPCX_DONE BIT(30)
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#define SHIM_IPCX_BUSY BIT(31)
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#define SHIM_BYT_IPCX_DONE BIT_ULL(62)
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#define SHIM_BYT_IPCX_BUSY BIT_ULL(63)
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/* IPCD */
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#define SHIM_IPCD_DONE BIT(30)
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#define SHIM_IPCD_BUSY BIT(31)
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#define SHIM_BYT_IPCD_DONE BIT_ULL(62)
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#define SHIM_BYT_IPCD_BUSY BIT_ULL(63)
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/* CLKCTL */
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#define SHIM_CLKCTL_SMOS(x) ((x) << 24)
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#define SHIM_CLKCTL_MASK (3 << 24)
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#define SHIM_CLKCTL_DCPLCG BIT(18)
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#define SHIM_CLKCTL_SCOE1 BIT(17)
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#define SHIM_CLKCTL_SCOE0 BIT(16)
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/* CSR2 / CS2 */
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#define SHIM_CSR2_SDFD_SSP0 BIT(1)
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#define SHIM_CSR2_SDFD_SSP1 BIT(2)
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/* LTRC */
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#define SHIM_LTRC_VAL(x) ((x) << 0)
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/* HMDC */
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#define SHIM_HMDC_HDDA0(x) ((x) << 0)
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#define SHIM_HMDC_HDDA1(x) ((x) << 7)
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#define SHIM_HMDC_HDDA_E0_CH0 1
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#define SHIM_HMDC_HDDA_E0_CH1 2
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#define SHIM_HMDC_HDDA_E0_CH2 4
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#define SHIM_HMDC_HDDA_E0_CH3 8
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#define SHIM_HMDC_HDDA_E1_CH0 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH0)
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#define SHIM_HMDC_HDDA_E1_CH1 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH1)
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#define SHIM_HMDC_HDDA_E1_CH2 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH2)
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#define SHIM_HMDC_HDDA_E1_CH3 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH3)
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#define SHIM_HMDC_HDDA_E0_ALLCH \
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(SHIM_HMDC_HDDA_E0_CH0 | SHIM_HMDC_HDDA_E0_CH1 | \
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SHIM_HMDC_HDDA_E0_CH2 | SHIM_HMDC_HDDA_E0_CH3)
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#define SHIM_HMDC_HDDA_E1_ALLCH \
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(SHIM_HMDC_HDDA_E1_CH0 | SHIM_HMDC_HDDA_E1_CH1 | \
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SHIM_HMDC_HDDA_E1_CH2 | SHIM_HMDC_HDDA_E1_CH3)
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/* Audio DSP PCI registers */
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#define PCI_VDRTCTL0 0xa0
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#define PCI_VDRTCTL1 0xa4
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#define PCI_VDRTCTL2 0xa8
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#define PCI_VDRTCTL3 0xaC
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/* VDRTCTL0 */
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#define PCI_VDRTCL0_D3PGD BIT(0)
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#define PCI_VDRTCL0_D3SRAMPGD BIT(1)
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#define PCI_VDRTCL0_DSRAMPGE_SHIFT 12
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#define PCI_VDRTCL0_DSRAMPGE_MASK GENMASK(PCI_VDRTCL0_DSRAMPGE_SHIFT + 19,\
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PCI_VDRTCL0_DSRAMPGE_SHIFT)
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#define PCI_VDRTCL0_ISRAMPGE_SHIFT 2
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#define PCI_VDRTCL0_ISRAMPGE_MASK GENMASK(PCI_VDRTCL0_ISRAMPGE_SHIFT + 9,\
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PCI_VDRTCL0_ISRAMPGE_SHIFT)
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/* VDRTCTL2 */
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#define PCI_VDRTCL2_DCLCGE BIT(1)
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#define PCI_VDRTCL2_DTCGE BIT(10)
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#define PCI_VDRTCL2_APLLSE_MASK BIT(31)
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/* PMCS */
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#define PCI_PMCS 0x84
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#define PCI_PMCS_PS_MASK 0x3
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/* DSP hardware descriptor */
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struct sof_intel_dsp_desc {
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int cores_num;
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int host_managed_cores_mask;
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int init_core_mask; /* cores available after fw boot */
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int ipc_req;
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int ipc_req_mask;
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int ipc_ack;
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int ipc_ack_mask;
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int ipc_ctl;
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int rom_status_reg;
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int rom_init_timeout;
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int ssp_count; /* ssp count of the platform */
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int ssp_base_offset; /* base address of the SSPs */
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u32 sdw_shim_base;
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u32 sdw_alh_base;
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bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
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};
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extern const struct snd_sof_dsp_ops sof_tng_ops;
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extern const struct sof_intel_dsp_desc tng_chip_info;
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struct sof_intel_stream {
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size_t posn_offset;
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};
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#endif
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