143 lines
5.9 KiB
C
143 lines
5.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Driver for Digigram miXart soundcards
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*
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* definitions and makros for basic card access
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*
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* Copyright (c) 2003 by Digigram <alsa@digigram.com>
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*/
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#ifndef __SOUND_MIXART_HWDEP_H
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#define __SOUND_MIXART_HWDEP_H
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#include <sound/hwdep.h>
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#ifndef readl_be
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#define readl_be(x) be32_to_cpu((__force __be32)__raw_readl(x))
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#endif
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#ifndef writel_be
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#define writel_be(data,addr) __raw_writel((__force u32)cpu_to_be32(data),addr)
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#endif
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#ifndef readl_le
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#define readl_le(x) le32_to_cpu((__force __le32)__raw_readl(x))
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#endif
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#ifndef writel_le
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#define writel_le(data,addr) __raw_writel((__force u32)cpu_to_le32(data),addr)
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#endif
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#define MIXART_MEM(mgr,x) ((mgr)->mem[0].virt + (x))
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#define MIXART_REG(mgr,x) ((mgr)->mem[1].virt + (x))
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/* Daughter board Type */
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#define DAUGHTER_TYPE_MASK 0x0F
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#define DAUGHTER_VER_MASK 0xF0
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#define DAUGHTER_TYPEVER_MASK (DAUGHTER_TYPE_MASK|DAUGHTER_VER_MASK)
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#define MIXART_DAUGHTER_TYPE_NONE 0x00
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#define MIXART_DAUGHTER_TYPE_COBRANET 0x08
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#define MIXART_DAUGHTER_TYPE_AES 0x0E
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#define MIXART_BA0_SIZE (16 * 1024 * 1024) /* 16M */
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#define MIXART_BA1_SIZE (4 * 1024) /* 4k */
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/*
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* -----------BAR 0 --------------------------------------------------------------------------------------------------------
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*/
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#define MIXART_PSEUDOREG 0x2000 /* base address for pseudoregister */
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#define MIXART_PSEUDOREG_BOARDNUMBER MIXART_PSEUDOREG+0 /* board number */
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/* perfmeter (available when elf loaded)*/
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#define MIXART_PSEUDOREG_PERF_STREAM_LOAD_OFFSET MIXART_PSEUDOREG+0x70 /* streaming load */
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#define MIXART_PSEUDOREG_PERF_SYSTEM_LOAD_OFFSET MIXART_PSEUDOREG+0x78 /* system load (reference)*/
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#define MIXART_PSEUDOREG_PERF_MAILBX_LOAD_OFFSET MIXART_PSEUDOREG+0x7C /* mailbox load */
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#define MIXART_PSEUDOREG_PERF_INTERR_LOAD_OFFSET MIXART_PSEUDOREG+0x74 /* interrupt handling load */
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/* motherboard xilinx loader info */
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#define MIXART_PSEUDOREG_MXLX_BASE_ADDR_OFFSET MIXART_PSEUDOREG+0x9C /* 0x00600000 */
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#define MIXART_PSEUDOREG_MXLX_SIZE_OFFSET MIXART_PSEUDOREG+0xA0 /* xilinx size in bytes */
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#define MIXART_PSEUDOREG_MXLX_STATUS_OFFSET MIXART_PSEUDOREG+0xA4 /* status = EMBEBBED_STAT_XXX */
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/* elf loader info */
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#define MIXART_PSEUDOREG_ELF_STATUS_OFFSET MIXART_PSEUDOREG+0xB0 /* status = EMBEBBED_STAT_XXX */
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/*
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* after the elf code is loaded, and the flowtable info was passed to it,
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* the driver polls on this address, until it shows 1 (presence) or 2 (absence)
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* once it is non-zero, the daughter board type may be read
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*/
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#define MIXART_PSEUDOREG_DBRD_PRESENCE_OFFSET MIXART_PSEUDOREG+0x990
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/* Global info structure */
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#define MIXART_PSEUDOREG_DBRD_TYPE_OFFSET MIXART_PSEUDOREG+0x994 /* Type and version of daughterboard */
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/* daughterboard xilinx loader info */
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#define MIXART_PSEUDOREG_DXLX_BASE_ADDR_OFFSET MIXART_PSEUDOREG+0x998 /* get the address here where to write the file */
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#define MIXART_PSEUDOREG_DXLX_SIZE_OFFSET MIXART_PSEUDOREG+0x99C /* xilinx size in bytes */
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#define MIXART_PSEUDOREG_DXLX_STATUS_OFFSET MIXART_PSEUDOREG+0x9A0 /* status = EMBEBBED_STAT_XXX */
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/* */
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#define MIXART_FLOWTABLE_PTR 0x3000 /* pointer to flow table */
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/* mailbox addresses */
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/* message DRV -> EMB */
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#define MSG_INBOUND_POST_HEAD 0x010008 /* DRV posts MF + increment4 */
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#define MSG_INBOUND_POST_TAIL 0x01000C /* EMB gets MF + increment4 */
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/* message EMB -> DRV */
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#define MSG_OUTBOUND_POST_TAIL 0x01001C /* DRV gets MF + increment4 */
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#define MSG_OUTBOUND_POST_HEAD 0x010018 /* EMB posts MF + increment4 */
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/* Get Free Frames */
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#define MSG_INBOUND_FREE_TAIL 0x010004 /* DRV gets MFA + increment4 */
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#define MSG_OUTBOUND_FREE_TAIL 0x010014 /* EMB gets MFA + increment4 */
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/* Put Free Frames */
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#define MSG_OUTBOUND_FREE_HEAD 0x010010 /* DRV puts MFA + increment4 */
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#define MSG_INBOUND_FREE_HEAD 0x010000 /* EMB puts MFA + increment4 */
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/* firmware addresses of the message fifos */
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#define MSG_BOUND_STACK_SIZE 0x004000 /* size of each following stack */
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/* posted messages */
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#define MSG_OUTBOUND_POST_STACK 0x108000 /* stack of messages to the DRV */
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#define MSG_INBOUND_POST_STACK 0x104000 /* stack of messages to the EMB */
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/* available empty messages */
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#define MSG_OUTBOUND_FREE_STACK 0x10C000 /* stack of free enveloped for EMB */
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#define MSG_INBOUND_FREE_STACK 0x100000 /* stack of free enveloped for DRV */
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/* defines for mailbox message frames */
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#define MSG_FRAME_OFFSET 0x64
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#define MSG_FRAME_SIZE 0x6400
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#define MSG_FRAME_NUMBER 32
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#define MSG_FROM_AGENT_ITMF_OFFSET (MSG_FRAME_OFFSET + (MSG_FRAME_SIZE * MSG_FRAME_NUMBER))
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#define MSG_TO_AGENT_ITMF_OFFSET (MSG_FROM_AGENT_ITMF_OFFSET + MSG_FRAME_SIZE)
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#define MSG_HOST_RSC_PROTECTION (MSG_TO_AGENT_ITMF_OFFSET + MSG_FRAME_SIZE)
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#define MSG_AGENT_RSC_PROTECTION (MSG_HOST_RSC_PROTECTION + 4)
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/*
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* -----------BAR 1 --------------------------------------------------------------------------------------------------------
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*/
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/* interrupt addresses and constants */
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#define MIXART_PCI_OMIMR_OFFSET 0x34 /* outbound message interrupt mask register */
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#define MIXART_PCI_OMISR_OFFSET 0x30 /* outbound message interrupt status register */
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#define MIXART_PCI_ODBR_OFFSET 0x60 /* outbound doorbell register */
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#define MIXART_BA1_BRUTAL_RESET_OFFSET 0x68 /* write 1 in LSBit to reset board */
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#define MIXART_HOST_ALL_INTERRUPT_MASKED 0x02B /* 0000 0010 1011 */
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#define MIXART_ALLOW_OUTBOUND_DOORBELL 0x023 /* 0000 0010 0011 */
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#define MIXART_OIDI 0x008 /* 0000 0000 1000 */
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int snd_mixart_setup_firmware(struct mixart_mgr *mgr);
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#endif /* __SOUND_MIXART_HWDEP_H */
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