43 lines
1.1 KiB
C
43 lines
1.1 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
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* Copyright (c) 2020 Western Digital Corporation or its affiliates.
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*/
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#ifndef RESET_K210_SYSCTL_H
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#define RESET_K210_SYSCTL_H
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/*
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* Kendryte K210 SoC system controller K210_SYSCTL_SOFT_RESET register bits.
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* Taken from Kendryte SDK (kendryte-standalone-sdk).
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*/
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#define K210_RST_ROM 0
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#define K210_RST_DMA 1
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#define K210_RST_AI 2
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#define K210_RST_DVP 3
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#define K210_RST_FFT 4
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#define K210_RST_GPIO 5
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#define K210_RST_SPI0 6
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#define K210_RST_SPI1 7
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#define K210_RST_SPI2 8
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#define K210_RST_SPI3 9
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#define K210_RST_I2S0 10
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#define K210_RST_I2S1 11
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#define K210_RST_I2S2 12
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#define K210_RST_I2C0 13
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#define K210_RST_I2C1 14
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#define K210_RST_I2C2 15
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#define K210_RST_UART1 16
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#define K210_RST_UART2 17
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#define K210_RST_UART3 18
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#define K210_RST_AES 19
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#define K210_RST_FPIOA 20
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#define K210_RST_TIMER0 21
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#define K210_RST_TIMER1 22
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#define K210_RST_TIMER2 23
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#define K210_RST_WDT0 24
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#define K210_RST_WDT1 25
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#define K210_RST_SHA 26
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#define K210_RST_RTC 29
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#endif /* RESET_K210_SYSCTL_H */
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