179 lines
4.4 KiB
C
179 lines
4.4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015 Hisilicon Limited.
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*
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* Author: Bintian Wang <bintian.wang@huawei.com>
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*/
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#ifndef __DT_BINDINGS_CLOCK_HI6220_H
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#define __DT_BINDINGS_CLOCK_HI6220_H
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/* clk in Hi6220 AO (always on) controller */
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#define HI6220_NONE_CLOCK 0
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/* fixed rate clocks */
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#define HI6220_REF32K 1
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#define HI6220_CLK_TCXO 2
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#define HI6220_MMC1_PAD 3
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#define HI6220_MMC2_PAD 4
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#define HI6220_MMC0_PAD 5
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#define HI6220_PLL_BBP 6
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#define HI6220_PLL_GPU 7
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#define HI6220_PLL1_DDR 8
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#define HI6220_PLL_SYS 9
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#define HI6220_PLL_SYS_MEDIA 10
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#define HI6220_DDR_SRC 11
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#define HI6220_PLL_MEDIA 12
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#define HI6220_PLL_DDR 13
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/* fixed factor clocks */
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#define HI6220_300M 14
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#define HI6220_150M 15
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#define HI6220_PICOPHY_SRC 16
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#define HI6220_MMC0_SRC_SEL 17
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#define HI6220_MMC1_SRC_SEL 18
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#define HI6220_MMC2_SRC_SEL 19
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#define HI6220_VPU_CODEC 20
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#define HI6220_MMC0_SMP 21
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#define HI6220_MMC1_SMP 22
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#define HI6220_MMC2_SMP 23
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/* gate clocks */
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#define HI6220_WDT0_PCLK 24
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#define HI6220_WDT1_PCLK 25
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#define HI6220_WDT2_PCLK 26
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#define HI6220_TIMER0_PCLK 27
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#define HI6220_TIMER1_PCLK 28
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#define HI6220_TIMER2_PCLK 29
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#define HI6220_TIMER3_PCLK 30
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#define HI6220_TIMER4_PCLK 31
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#define HI6220_TIMER5_PCLK 32
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#define HI6220_TIMER6_PCLK 33
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#define HI6220_TIMER7_PCLK 34
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#define HI6220_TIMER8_PCLK 35
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#define HI6220_UART0_PCLK 36
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#define HI6220_RTC0_PCLK 37
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#define HI6220_RTC1_PCLK 38
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#define HI6220_AO_NR_CLKS 39
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/* clk in Hi6220 systrl */
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/* gate clock */
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#define HI6220_MMC0_CLK 1
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#define HI6220_MMC0_CIUCLK 2
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#define HI6220_MMC1_CLK 3
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#define HI6220_MMC1_CIUCLK 4
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#define HI6220_MMC2_CLK 5
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#define HI6220_MMC2_CIUCLK 6
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#define HI6220_USBOTG_HCLK 7
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#define HI6220_CLK_PICOPHY 8
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#define HI6220_HIFI 9
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#define HI6220_DACODEC_PCLK 10
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#define HI6220_EDMAC_ACLK 11
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#define HI6220_CS_ATB 12
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#define HI6220_I2C0_CLK 13
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#define HI6220_I2C1_CLK 14
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#define HI6220_I2C2_CLK 15
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#define HI6220_I2C3_CLK 16
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#define HI6220_UART1_PCLK 17
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#define HI6220_UART2_PCLK 18
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#define HI6220_UART3_PCLK 19
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#define HI6220_UART4_PCLK 20
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#define HI6220_SPI_CLK 21
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#define HI6220_TSENSOR_CLK 22
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#define HI6220_MMU_CLK 23
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#define HI6220_HIFI_SEL 24
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#define HI6220_MMC0_SYSPLL 25
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#define HI6220_MMC1_SYSPLL 26
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#define HI6220_MMC2_SYSPLL 27
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#define HI6220_MMC0_SEL 28
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#define HI6220_MMC1_SEL 29
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#define HI6220_BBPPLL_SEL 30
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#define HI6220_MEDIA_PLL_SRC 31
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#define HI6220_MMC2_SEL 32
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#define HI6220_CS_ATB_SYSPLL 33
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/* mux clocks */
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#define HI6220_MMC0_SRC 34
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#define HI6220_MMC0_SMP_IN 35
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#define HI6220_MMC1_SRC 36
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#define HI6220_MMC1_SMP_IN 37
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#define HI6220_MMC2_SRC 38
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#define HI6220_MMC2_SMP_IN 39
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#define HI6220_HIFI_SRC 40
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#define HI6220_UART1_SRC 41
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#define HI6220_UART2_SRC 42
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#define HI6220_UART3_SRC 43
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#define HI6220_UART4_SRC 44
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#define HI6220_MMC0_MUX0 45
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#define HI6220_MMC1_MUX0 46
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#define HI6220_MMC2_MUX0 47
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#define HI6220_MMC0_MUX1 48
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#define HI6220_MMC1_MUX1 49
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#define HI6220_MMC2_MUX1 50
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/* divider clocks */
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#define HI6220_CLK_BUS 51
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#define HI6220_MMC0_DIV 52
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#define HI6220_MMC1_DIV 53
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#define HI6220_MMC2_DIV 54
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#define HI6220_HIFI_DIV 55
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#define HI6220_BBPPLL0_DIV 56
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#define HI6220_CS_DAPB 57
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#define HI6220_CS_ATB_DIV 58
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/* gate clock */
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#define HI6220_DAPB_CLK 59
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#define HI6220_SYS_NR_CLKS 60
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/* clk in Hi6220 media controller */
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/* gate clocks */
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#define HI6220_DSI_PCLK 1
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#define HI6220_G3D_PCLK 2
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#define HI6220_ACLK_CODEC_VPU 3
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#define HI6220_ISP_SCLK 4
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#define HI6220_ADE_CORE 5
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#define HI6220_MED_MMU 6
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#define HI6220_CFG_CSI4PHY 7
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#define HI6220_CFG_CSI2PHY 8
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#define HI6220_ISP_SCLK_GATE 9
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#define HI6220_ISP_SCLK_GATE1 10
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#define HI6220_ADE_CORE_GATE 11
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#define HI6220_CODEC_VPU_GATE 12
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#define HI6220_MED_SYSPLL 13
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/* mux clocks */
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#define HI6220_1440_1200 14
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#define HI6220_1000_1200 15
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#define HI6220_1000_1440 16
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/* divider clocks */
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#define HI6220_CODEC_JPEG 17
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#define HI6220_ISP_SCLK_SRC 18
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#define HI6220_ISP_SCLK1 19
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#define HI6220_ADE_CORE_SRC 20
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#define HI6220_ADE_PIX_SRC 21
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#define HI6220_G3D_CLK 22
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#define HI6220_CODEC_VPU_SRC 23
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#define HI6220_MEDIA_NR_CLKS 24
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/* clk in Hi6220 power controller */
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/* gate clocks */
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#define HI6220_PLL_GPU_GATE 1
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#define HI6220_PLL1_DDR_GATE 2
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#define HI6220_PLL_DDR_GATE 3
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#define HI6220_PLL_MEDIA_GATE 4
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#define HI6220_PLL0_BBP_GATE 5
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/* divider clocks */
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#define HI6220_DDRC_SRC 6
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#define HI6220_DDRC_AXI1 7
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#define HI6220_POWER_NR_CLKS 8
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/* clk in Hi6220 acpu sctrl */
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#define HI6220_ACPU_SFT_AT_S 0
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#endif
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