95 lines
3.2 KiB
C
95 lines
3.2 KiB
C
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/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "rv770d.h"
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/**
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* rv770_copy_dma - copy pages using the DMA engine
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*
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* @rdev: radeon_device pointer
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* @src_offset: src GPU address
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* @dst_offset: dst GPU address
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* @num_gpu_pages: number of GPU pages to xfer
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* @resv: reservation object to sync to
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*
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* Copy GPU paging using the DMA engine (r7xx).
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* Used by the radeon ttm implementation to move pages if
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* registered as the asic copy callback.
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*/
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struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev,
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uint64_t src_offset, uint64_t dst_offset,
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unsigned num_gpu_pages,
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struct dma_resv *resv)
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{
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struct radeon_fence *fence;
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struct radeon_sync sync;
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int ring_index = rdev->asic->copy.dma_ring_index;
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struct radeon_ring *ring = &rdev->ring[ring_index];
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u32 size_in_dw, cur_size_in_dw;
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int i, num_loops;
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int r = 0;
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radeon_sync_create(&sync);
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size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
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num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFF);
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r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
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if (r) {
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DRM_ERROR("radeon: moving bo (%d).\n", r);
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radeon_sync_free(rdev, &sync, NULL);
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return ERR_PTR(r);
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}
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radeon_sync_resv(rdev, &sync, resv, false);
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radeon_sync_rings(rdev, &sync, ring->idx);
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for (i = 0; i < num_loops; i++) {
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cur_size_in_dw = size_in_dw;
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if (cur_size_in_dw > 0xFFFF)
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cur_size_in_dw = 0xFFFF;
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size_in_dw -= cur_size_in_dw;
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
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radeon_ring_write(ring, dst_offset & 0xfffffffc);
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radeon_ring_write(ring, src_offset & 0xfffffffc);
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radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
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radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
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src_offset += cur_size_in_dw * 4;
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dst_offset += cur_size_in_dw * 4;
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}
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r = radeon_fence_emit(rdev, &fence, ring->idx);
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if (r) {
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radeon_ring_unlock_undo(rdev, ring);
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radeon_sync_free(rdev, &sync, NULL);
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return ERR_PTR(r);
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}
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radeon_ring_unlock_commit(rdev, ring, false);
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radeon_sync_free(rdev, &sync, fence);
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return fence;
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}
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