419 lines
11 KiB
C
419 lines
11 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
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*/
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#ifndef __ADRENO_GPU_H__
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#define __ADRENO_GPU_H__
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#include <linux/firmware.h>
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#include <linux/iopoll.h>
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#include "msm_gpu.h"
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#include "adreno_common.xml.h"
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#include "adreno_pm4.xml.h"
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extern bool snapshot_debugbus;
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extern bool allow_vram_carveout;
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enum {
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ADRENO_FW_PM4 = 0,
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ADRENO_FW_SQE = 0, /* a6xx */
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ADRENO_FW_PFP = 1,
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ADRENO_FW_GMU = 1, /* a6xx */
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ADRENO_FW_GPMU = 2,
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ADRENO_FW_MAX,
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};
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#define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
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#define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
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#define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
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struct adreno_rev {
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uint8_t core;
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uint8_t major;
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uint8_t minor;
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uint8_t patchid;
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};
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#define ANY_ID 0xff
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#define ADRENO_REV(core, major, minor, patchid) \
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((struct adreno_rev){ core, major, minor, patchid })
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struct adreno_gpu_funcs {
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struct msm_gpu_funcs base;
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int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
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};
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struct adreno_reglist {
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u32 offset;
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u32 value;
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};
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extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
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struct adreno_info {
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struct adreno_rev rev;
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uint32_t revn;
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const char *name;
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const char *fw[ADRENO_FW_MAX];
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uint32_t gmem;
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u64 quirks;
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struct msm_gpu *(*init)(struct drm_device *dev);
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const char *zapfw;
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u32 inactive_period;
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const struct adreno_reglist *hwcg;
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};
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const struct adreno_info *adreno_info(struct adreno_rev rev);
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struct adreno_gpu {
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struct msm_gpu base;
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struct adreno_rev rev;
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const struct adreno_info *info;
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uint32_t gmem; /* actual gmem size */
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uint32_t revn; /* numeric revision name */
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const struct adreno_gpu_funcs *funcs;
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/* interesting register offsets to dump: */
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const unsigned int *registers;
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/*
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* Are we loading fw from legacy path? Prior to addition
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* of gpu firmware to linux-firmware, the fw files were
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* placed in toplevel firmware directory, following qcom's
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* android kernel. But linux-firmware preferred they be
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* placed in a 'qcom' subdirectory.
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*
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* For backwards compatibility, we try first to load from
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* the new path, using request_firmware_direct() to avoid
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* any potential timeout waiting for usermode helper, then
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* fall back to the old path (with direct load). And
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* finally fall back to request_firmware() with the new
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* path to allow the usermode helper.
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*/
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enum {
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FW_LOCATION_UNKNOWN = 0,
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FW_LOCATION_NEW, /* /lib/firmware/qcom/$fwfile */
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FW_LOCATION_LEGACY, /* /lib/firmware/$fwfile */
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FW_LOCATION_HELPER,
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} fwloc;
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/* firmware: */
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const struct firmware *fw[ADRENO_FW_MAX];
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/*
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* Register offsets are different between some GPUs.
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* GPU specific offsets will be exported by GPU specific
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* code (a3xx_gpu.c) and stored in this common location.
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*/
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const unsigned int *reg_offsets;
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};
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#define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
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struct adreno_ocmem {
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struct ocmem *ocmem;
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unsigned long base;
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void *hdl;
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};
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/* platform config data (ie. from DT, or pdata) */
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struct adreno_platform_config {
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struct adreno_rev rev;
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};
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#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
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#define spin_until(X) ({ \
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int __ret = -ETIMEDOUT; \
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unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
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do { \
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if (X) { \
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__ret = 0; \
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break; \
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} \
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} while (time_before(jiffies, __t)); \
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__ret; \
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})
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bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
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static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
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{
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return (gpu->revn < 300);
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}
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static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
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{
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return (gpu->revn < 210);
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}
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static inline bool adreno_is_a225(struct adreno_gpu *gpu)
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{
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return gpu->revn == 225;
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}
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static inline bool adreno_is_a305(struct adreno_gpu *gpu)
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{
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return gpu->revn == 305;
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}
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static inline bool adreno_is_a306(struct adreno_gpu *gpu)
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{
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/* yes, 307, because a305c is 306 */
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return gpu->revn == 307;
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}
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static inline bool adreno_is_a320(struct adreno_gpu *gpu)
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{
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return gpu->revn == 320;
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}
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static inline bool adreno_is_a330(struct adreno_gpu *gpu)
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{
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return gpu->revn == 330;
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}
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static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
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{
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return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
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}
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static inline int adreno_is_a405(struct adreno_gpu *gpu)
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{
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return gpu->revn == 405;
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}
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static inline int adreno_is_a420(struct adreno_gpu *gpu)
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{
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return gpu->revn == 420;
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}
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static inline int adreno_is_a430(struct adreno_gpu *gpu)
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{
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return gpu->revn == 430;
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}
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static inline int adreno_is_a508(struct adreno_gpu *gpu)
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{
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return gpu->revn == 508;
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}
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static inline int adreno_is_a509(struct adreno_gpu *gpu)
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{
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return gpu->revn == 509;
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}
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static inline int adreno_is_a510(struct adreno_gpu *gpu)
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{
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return gpu->revn == 510;
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}
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static inline int adreno_is_a512(struct adreno_gpu *gpu)
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{
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return gpu->revn == 512;
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}
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static inline int adreno_is_a530(struct adreno_gpu *gpu)
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{
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return gpu->revn == 530;
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}
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static inline int adreno_is_a540(struct adreno_gpu *gpu)
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{
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return gpu->revn == 540;
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}
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static inline int adreno_is_a618(struct adreno_gpu *gpu)
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{
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return gpu->revn == 618;
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}
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static inline int adreno_is_a630(struct adreno_gpu *gpu)
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{
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return gpu->revn == 630;
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}
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static inline int adreno_is_a640_family(struct adreno_gpu *gpu)
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{
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return (gpu->revn == 640) || (gpu->revn == 680);
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}
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static inline int adreno_is_a650(struct adreno_gpu *gpu)
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{
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return gpu->revn == 650;
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}
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static inline int adreno_is_7c3(struct adreno_gpu *gpu)
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{
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/* The order of args is important here to handle ANY_ID correctly */
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return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
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}
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static inline int adreno_is_a660(struct adreno_gpu *gpu)
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{
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return gpu->revn == 660;
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}
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static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
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{
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return adreno_is_a660(gpu) || adreno_is_7c3(gpu);
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}
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/* check for a650, a660, or any derivatives */
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static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
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{
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return gpu->revn == 650 || gpu->revn == 620 ||
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adreno_is_a660_family(gpu);
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}
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int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
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const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
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const char *fwname);
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struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
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const struct firmware *fw, u64 *iova);
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int adreno_hw_init(struct msm_gpu *gpu);
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void adreno_recover(struct msm_gpu *gpu);
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void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
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bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
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#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
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void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
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struct drm_printer *p);
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#endif
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void adreno_dump_info(struct msm_gpu *gpu);
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void adreno_dump(struct msm_gpu *gpu);
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void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
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struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
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int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
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struct adreno_ocmem *ocmem);
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void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
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int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
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struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
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int nr_rings);
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void adreno_gpu_cleanup(struct adreno_gpu *gpu);
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int adreno_load_fw(struct adreno_gpu *adreno_gpu);
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void adreno_gpu_state_destroy(struct msm_gpu_state *state);
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int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
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int adreno_gpu_state_put(struct msm_gpu_state *state);
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/*
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* Common helper function to initialize the default address space for arm-smmu
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* attached targets
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*/
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struct msm_gem_address_space *
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adreno_iommu_create_address_space(struct msm_gpu *gpu,
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struct platform_device *pdev);
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void adreno_set_llc_attributes(struct iommu_domain *iommu);
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/*
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* For a5xx and a6xx targets load the zap shader that is used to pull the GPU
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* out of secure mode
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*/
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int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
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/* ringbuffer helpers (the parts that are adreno specific) */
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static inline void
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OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
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{
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adreno_wait_ring(ring, cnt+1);
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OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
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}
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/* no-op packet: */
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static inline void
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OUT_PKT2(struct msm_ringbuffer *ring)
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{
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adreno_wait_ring(ring, 1);
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OUT_RING(ring, CP_TYPE2_PKT);
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}
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static inline void
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OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
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{
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adreno_wait_ring(ring, cnt+1);
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OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
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}
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static inline u32 PM4_PARITY(u32 val)
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{
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return (0x9669 >> (0xF & (val ^
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(val >> 4) ^ (val >> 8) ^ (val >> 12) ^
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(val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
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(val >> 28)))) & 1;
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}
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/* Maximum number of values that can be executed for one opcode */
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#define TYPE4_MAX_PAYLOAD 127
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#define PKT4(_reg, _cnt) \
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(CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
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(((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
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static inline void
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OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
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{
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adreno_wait_ring(ring, cnt + 1);
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OUT_RING(ring, PKT4(regindx, cnt));
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}
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|
|
static inline void
|
||
|
|
OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
|
||
|
|
{
|
||
|
|
adreno_wait_ring(ring, cnt + 1);
|
||
|
|
OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
|
||
|
|
((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
|
||
|
|
}
|
||
|
|
|
||
|
|
struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
|
||
|
|
struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
|
||
|
|
struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
|
||
|
|
struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
|
||
|
|
struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
|
||
|
|
|
||
|
|
static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
|
||
|
|
{
|
||
|
|
return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Given a register and a count, return a value to program into
|
||
|
|
* REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
|
||
|
|
* registers starting at _reg.
|
||
|
|
*
|
||
|
|
* The register base needs to be a multiple of the length. If it is not, the
|
||
|
|
* hardware will quietly mask off the bits for you and shift the size. For
|
||
|
|
* example, if you intend the protection to start at 0x07 for a length of 4
|
||
|
|
* (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
|
||
|
|
* expose registers you intended to protect!
|
||
|
|
*/
|
||
|
|
#define ADRENO_PROTECT_RW(_reg, _len) \
|
||
|
|
((1 << 30) | (1 << 29) | \
|
||
|
|
((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Same as above, but allow reads over the range. For areas of mixed use (such
|
||
|
|
* as performance counters) this allows us to protect a much larger range with a
|
||
|
|
* single register
|
||
|
|
*/
|
||
|
|
#define ADRENO_PROTECT_RDONLY(_reg, _len) \
|
||
|
|
((1 << 29) \
|
||
|
|
((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
|
||
|
|
|
||
|
|
|
||
|
|
#define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
|
||
|
|
readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
|
||
|
|
interval, timeout)
|
||
|
|
|
||
|
|
#endif /* __ADRENO_GPU_H__ */
|