272 lines
11 KiB
C
272 lines
11 KiB
C
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/* Copyright 2012-17 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_DWBC_DCN10_H__
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#define __DC_DWBC_DCN10_H__
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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/* DCN */
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#define BASE_INNER(seg) \
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DCE_BASE__INST0_SEG ## seg
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#define BASE(seg) \
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BASE_INNER(seg)
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#define SR(reg_name)\
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.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
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mm ## reg_name
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#define SRI(reg_name, block, id)\
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.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
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mm ## block ## id ## _ ## reg_name
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#define SRII(reg_name, block, id)\
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.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
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mm ## block ## id ## _ ## reg_name
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#define SF(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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#define DWBC_COMMON_REG_LIST_DCN1_0(inst) \
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SRI(WB_ENABLE, CNV, inst),\
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SRI(WB_EC_CONFIG, CNV, inst),\
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SRI(CNV_MODE, CNV, inst),\
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SRI(WB_SOFT_RESET, CNV, inst),\
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SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
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SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
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SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
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SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
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SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
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SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
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SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
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SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
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SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst)
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#define DWBC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh) \
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SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
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SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
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SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
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SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
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SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
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SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
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SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
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SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
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SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
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SF(CNV0_CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
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SF(CNV0_CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
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SF(CNV0_CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
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SF(CNV0_CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
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SF(CNV0_CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
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SF(CNV0_CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
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SF(CNV0_WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_DUALSIZE_REQ, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
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SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh)
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#define DWBC_REG_FIELD_LIST(type) \
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type WB_ENABLE;\
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type DISPCLK_R_WB_GATE_DIS;\
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type DISPCLK_G_WB_GATE_DIS;\
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type DISPCLK_G_WBSCL_GATE_DIS;\
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type WB_LB_LS_DIS;\
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type WB_LB_SD_DIS;\
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type WB_LUT_LS_DIS;\
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type CNV_WINDOW_CROP_EN;\
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type CNV_STEREO_TYPE;\
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type CNV_INTERLACED_MODE;\
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type CNV_EYE_SELECTION;\
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type CNV_STEREO_POLARITY;\
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type CNV_INTERLACED_FIELD_ORDER;\
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type CNV_STEREO_SPLIT;\
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type CNV_NEW_CONTENT;\
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type CNV_FRAME_CAPTURE_EN;\
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type WB_SOFT_RESET;\
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type MCIF_WB_BUFMGR_ENABLE;\
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type MCIF_WB_BUF_DUALSIZE_REQ;\
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type MCIF_WB_BUFMGR_SW_INT_EN;\
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type MCIF_WB_BUFMGR_SW_INT_ACK;\
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type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\
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type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\
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type MCIF_WB_BUFMGR_SW_LOCK;\
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type MCIF_WB_P_VMID;\
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type MCIF_WB_BUF_ADDR_FENCE_EN;\
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type MCIF_WB_BUF_LUMA_PITCH;\
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type MCIF_WB_BUF_CHROMA_PITCH;\
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type MCIF_WB_CLIENT_ARBITRATION_SLICE;\
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type MCIF_WB_TIME_PER_PIXEL;\
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type WM_CHANGE_ACK_FORCE_ON;\
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type MCIF_WB_CLI_WATERMARK_MASK;\
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type MCIF_WB_BUF_1_ADDR_Y;\
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type MCIF_WB_BUF_1_ADDR_Y_OFFSET;\
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type MCIF_WB_BUF_1_ADDR_C;\
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type MCIF_WB_BUF_1_ADDR_C_OFFSET;\
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type MCIF_WB_BUF_2_ADDR_Y;\
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type MCIF_WB_BUF_2_ADDR_Y_OFFSET;\
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type MCIF_WB_BUF_2_ADDR_C;\
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type MCIF_WB_BUF_2_ADDR_C_OFFSET;\
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type MCIF_WB_BUF_3_ADDR_Y;\
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type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\
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type MCIF_WB_BUF_3_ADDR_C;\
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type MCIF_WB_BUF_3_ADDR_C_OFFSET;\
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type MCIF_WB_BUF_4_ADDR_Y;\
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type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\
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type MCIF_WB_BUF_4_ADDR_C;\
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type MCIF_WB_BUF_4_ADDR_C_OFFSET;\
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type MCIF_WB_BUFMGR_VCE_LOCK_IGNORE;\
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type MCIF_WB_BUFMGR_VCE_INT_EN;\
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type MCIF_WB_BUFMGR_VCE_INT_ACK;\
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type MCIF_WB_BUFMGR_VCE_SLICE_INT_EN;\
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type MCIF_WB_BUFMGR_VCE_LOCK;\
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type MCIF_WB_BUFMGR_SLICE_SIZE;\
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type NB_PSTATE_CHANGE_REFRESH_WATERMARK;\
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type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST;\
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type NB_PSTATE_CHANGE_FORCE_ON;\
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type NB_PSTATE_ALLOW_FOR_URGENT;\
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type NB_PSTATE_CHANGE_WATERMARK_MASK;\
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type MCIF_WB_CLI_WATERMARK;\
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type MCIF_WB_CLI_CLOCK_GATER_OVERRIDE;\
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type MCIF_WB_PITCH_SIZE_WARMUP;\
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type MCIF_WB_BUF_LUMA_SIZE;\
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type MCIF_WB_BUF_CHROMA_SIZE;\
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struct dcn10_dwbc_registers {
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uint32_t WB_ENABLE;
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uint32_t WB_EC_CONFIG;
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uint32_t CNV_MODE;
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uint32_t WB_SOFT_RESET;
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uint32_t MCIF_WB_BUFMGR_SW_CONTROL;
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uint32_t MCIF_WB_BUF_PITCH;
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uint32_t MCIF_WB_ARBITRATION_CONTROL;
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uint32_t MCIF_WB_SCLK_CHANGE;
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uint32_t MCIF_WB_BUF_1_ADDR_Y;
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uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;
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uint32_t MCIF_WB_BUF_1_ADDR_C;
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uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;
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uint32_t MCIF_WB_BUF_2_ADDR_Y;
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uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;
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uint32_t MCIF_WB_BUF_2_ADDR_C;
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uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;
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uint32_t MCIF_WB_BUF_3_ADDR_Y;
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uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;
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uint32_t MCIF_WB_BUF_3_ADDR_C;
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uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;
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uint32_t MCIF_WB_BUF_4_ADDR_Y;
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uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;
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uint32_t MCIF_WB_BUF_4_ADDR_C;
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uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;
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uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;
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uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;
|
||
|
|
uint32_t MCIF_WB_NB_PSTATE_CONTROL;
|
||
|
|
uint32_t MCIF_WB_WATERMARK;
|
||
|
|
uint32_t MCIF_WB_WARM_UP_CNTL;
|
||
|
|
uint32_t MCIF_WB_BUF_LUMA_SIZE;
|
||
|
|
uint32_t MCIF_WB_BUF_CHROMA_SIZE;
|
||
|
|
};
|
||
|
|
struct dcn10_dwbc_mask {
|
||
|
|
DWBC_REG_FIELD_LIST(uint32_t)
|
||
|
|
};
|
||
|
|
struct dcn10_dwbc_shift {
|
||
|
|
DWBC_REG_FIELD_LIST(uint8_t)
|
||
|
|
};
|
||
|
|
struct dcn10_dwbc {
|
||
|
|
struct dwbc base;
|
||
|
|
const struct dcn10_dwbc_registers *dwbc_regs;
|
||
|
|
const struct dcn10_dwbc_shift *dwbc_shift;
|
||
|
|
const struct dcn10_dwbc_mask *dwbc_mask;
|
||
|
|
};
|
||
|
|
|
||
|
|
void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
|
||
|
|
struct dc_context *ctx,
|
||
|
|
const struct dcn10_dwbc_registers *dwbc_regs,
|
||
|
|
const struct dcn10_dwbc_shift *dwbc_shift,
|
||
|
|
const struct dcn10_dwbc_mask *dwbc_mask,
|
||
|
|
int inst);
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif
|