249 lines
7.3 KiB
C
249 lines
7.3 KiB
C
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// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
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/* Copyright(c) 2014 - 2020 Intel Corporation */
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#include <adf_accel_devices.h>
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#include <adf_pf2vf_msg.h>
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#include <adf_common_drv.h>
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#include <adf_gen2_hw_data.h>
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#include "adf_dh895xcc_hw_data.h"
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#include "icp_qat_hw.h"
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/* Worker thread to service arbiter mappings */
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static const u32 thrd_to_arb_map[ADF_DH895XCC_MAX_ACCELENGINES] = {
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0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
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0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
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0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222
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};
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static struct adf_hw_device_class dh895xcc_class = {
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.name = ADF_DH895XCC_DEVICE_NAME,
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.type = DEV_DH895XCC,
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.instances = 0
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};
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static u32 get_accel_mask(struct adf_hw_device_data *self)
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{
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u32 fuses = self->fuses;
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return ~fuses >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET &
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ADF_DH895XCC_ACCELERATORS_MASK;
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}
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static u32 get_ae_mask(struct adf_hw_device_data *self)
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{
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u32 fuses = self->fuses;
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return ~fuses & ADF_DH895XCC_ACCELENGINES_MASK;
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}
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static u32 get_num_accels(struct adf_hw_device_data *self)
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{
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u32 i, ctr = 0;
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if (!self || !self->accel_mask)
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return 0;
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for (i = 0; i < ADF_DH895XCC_MAX_ACCELERATORS; i++) {
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if (self->accel_mask & (1 << i))
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ctr++;
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}
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return ctr;
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}
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static u32 get_num_aes(struct adf_hw_device_data *self)
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{
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u32 i, ctr = 0;
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if (!self || !self->ae_mask)
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return 0;
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for (i = 0; i < ADF_DH895XCC_MAX_ACCELENGINES; i++) {
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if (self->ae_mask & (1 << i))
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ctr++;
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}
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return ctr;
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}
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static u32 get_misc_bar_id(struct adf_hw_device_data *self)
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{
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return ADF_DH895XCC_PMISC_BAR;
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}
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static u32 get_etr_bar_id(struct adf_hw_device_data *self)
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{
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return ADF_DH895XCC_ETR_BAR;
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}
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static u32 get_sram_bar_id(struct adf_hw_device_data *self)
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{
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return ADF_DH895XCC_SRAM_BAR;
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}
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static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
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{
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struct pci_dev *pdev = accel_dev->accel_pci_dev.pci_dev;
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u32 capabilities;
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u32 legfuses;
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capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
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ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
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ICP_ACCEL_CAPABILITIES_AUTHENTICATION |
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ICP_ACCEL_CAPABILITIES_CIPHER |
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ICP_ACCEL_CAPABILITIES_COMPRESSION;
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/* Read accelerator capabilities mask */
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pci_read_config_dword(pdev, ADF_DEVICE_LEGFUSE_OFFSET, &legfuses);
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/* A set bit in legfuses means the feature is OFF in this SKU */
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if (legfuses & ICP_ACCEL_MASK_CIPHER_SLICE) {
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capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
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capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
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}
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if (legfuses & ICP_ACCEL_MASK_PKE_SLICE)
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capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
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if (legfuses & ICP_ACCEL_MASK_AUTH_SLICE) {
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capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
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capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
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}
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if (legfuses & ICP_ACCEL_MASK_COMPRESS_SLICE)
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capabilities &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
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return capabilities;
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}
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static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
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{
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int sku = (self->fuses & ADF_DH895XCC_FUSECTL_SKU_MASK)
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>> ADF_DH895XCC_FUSECTL_SKU_SHIFT;
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switch (sku) {
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case ADF_DH895XCC_FUSECTL_SKU_1:
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return DEV_SKU_1;
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case ADF_DH895XCC_FUSECTL_SKU_2:
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return DEV_SKU_2;
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case ADF_DH895XCC_FUSECTL_SKU_3:
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return DEV_SKU_3;
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case ADF_DH895XCC_FUSECTL_SKU_4:
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return DEV_SKU_4;
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default:
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return DEV_SKU_UNKNOWN;
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}
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return DEV_SKU_UNKNOWN;
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}
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static const u32 *adf_get_arbiter_mapping(void)
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{
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return thrd_to_arb_map;
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}
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static u32 get_pf2vf_offset(u32 i)
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{
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return ADF_DH895XCC_PF2VF_OFFSET(i);
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}
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static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
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{
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struct adf_hw_device_data *hw_device = accel_dev->hw_device;
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struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_DH895XCC_PMISC_BAR];
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unsigned long accel_mask = hw_device->accel_mask;
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unsigned long ae_mask = hw_device->ae_mask;
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void __iomem *csr = misc_bar->virt_addr;
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unsigned int val, i;
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/* Enable Accel Engine error detection & correction */
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for_each_set_bit(i, &ae_mask, GET_MAX_ACCELENGINES(accel_dev)) {
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val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i));
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val |= ADF_DH895XCC_ENABLE_AE_ECC_ERR;
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ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val);
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val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i));
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val |= ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR;
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ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val);
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}
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/* Enable shared memory error detection & correction */
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for_each_set_bit(i, &accel_mask, ADF_DH895XCC_MAX_ACCELERATORS) {
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val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i));
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val |= ADF_DH895XCC_ERRSSMSH_EN;
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ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val);
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val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i));
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val |= ADF_DH895XCC_ERRSSMSH_EN;
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ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val);
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}
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}
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static void adf_enable_ints(struct adf_accel_dev *accel_dev)
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{
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void __iomem *addr;
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addr = (&GET_BARS(accel_dev)[ADF_DH895XCC_PMISC_BAR])->virt_addr;
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/* Enable bundle and misc interrupts */
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ADF_CSR_WR(addr, ADF_DH895XCC_SMIAPF0_MASK_OFFSET,
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accel_dev->pf.vf_info ? 0 :
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BIT_ULL(GET_MAX_BANKS(accel_dev)) - 1);
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ADF_CSR_WR(addr, ADF_DH895XCC_SMIAPF1_MASK_OFFSET,
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ADF_DH895XCC_SMIA1_MASK);
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}
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static int adf_enable_pf2vf_comms(struct adf_accel_dev *accel_dev)
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{
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spin_lock_init(&accel_dev->pf.vf2pf_ints_lock);
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return 0;
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}
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static void configure_iov_threads(struct adf_accel_dev *accel_dev, bool enable)
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{
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adf_gen2_cfg_iov_thds(accel_dev, enable,
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ADF_DH895XCC_AE2FUNC_MAP_GRP_A_NUM_REGS,
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ADF_DH895XCC_AE2FUNC_MAP_GRP_B_NUM_REGS);
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}
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void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
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{
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hw_data->dev_class = &dh895xcc_class;
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hw_data->instance_id = dh895xcc_class.instances++;
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hw_data->num_banks = ADF_DH895XCC_ETR_MAX_BANKS;
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hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;
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hw_data->num_accel = ADF_DH895XCC_MAX_ACCELERATORS;
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hw_data->num_logical_accel = 1;
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hw_data->num_engines = ADF_DH895XCC_MAX_ACCELENGINES;
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hw_data->tx_rx_gap = ADF_DH895XCC_RX_RINGS_OFFSET;
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hw_data->tx_rings_mask = ADF_DH895XCC_TX_RINGS_MASK;
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hw_data->alloc_irq = adf_isr_resource_alloc;
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hw_data->free_irq = adf_isr_resource_free;
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hw_data->enable_error_correction = adf_enable_error_correction;
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hw_data->get_accel_mask = get_accel_mask;
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hw_data->get_ae_mask = get_ae_mask;
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hw_data->get_accel_cap = get_accel_cap;
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hw_data->get_num_accels = get_num_accels;
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hw_data->get_num_aes = get_num_aes;
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hw_data->get_etr_bar_id = get_etr_bar_id;
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hw_data->get_misc_bar_id = get_misc_bar_id;
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hw_data->get_admin_info = adf_gen2_get_admin_info;
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hw_data->get_arb_info = adf_gen2_get_arb_info;
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hw_data->get_sram_bar_id = get_sram_bar_id;
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hw_data->get_sku = get_sku;
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hw_data->fw_name = ADF_DH895XCC_FW;
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hw_data->fw_mmp_name = ADF_DH895XCC_MMP;
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hw_data->init_admin_comms = adf_init_admin_comms;
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hw_data->exit_admin_comms = adf_exit_admin_comms;
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hw_data->configure_iov_threads = configure_iov_threads;
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hw_data->send_admin_init = adf_send_admin_init;
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hw_data->init_arb = adf_init_arb;
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hw_data->exit_arb = adf_exit_arb;
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hw_data->get_arb_mapping = adf_get_arbiter_mapping;
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hw_data->enable_ints = adf_enable_ints;
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hw_data->reset_device = adf_reset_sbr;
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hw_data->get_pf2vf_offset = get_pf2vf_offset;
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hw_data->enable_pfvf_comms = adf_enable_pf2vf_comms;
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hw_data->disable_iov = adf_disable_sriov;
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hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION;
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adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
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}
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void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
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{
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hw_data->dev_class->instances--;
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}
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