1008 lines
26 KiB
ArmAsm
1008 lines
26 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* linux/boot/head.S
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*
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* Copyright (C) 1991, 1992, 1993 Linus Torvalds
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*/
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/*
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* head.S contains the 32-bit startup code.
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*
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* NOTE!!! Startup happens at absolute address 0x00001000, which is also where
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* the page directory will exist. The startup code will be overwritten by
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* the page directory. [According to comments etc elsewhere on a compressed
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* kernel it will end up at 0x1000 + 1Mb I hope so as I assume this. - AC]
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*
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* Page 0 is deliberately kept safe, since System Management Mode code in
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* laptops may need to access the BIOS data stored there. This is also
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* useful for future device drivers that either access the BIOS via VM86
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* mode.
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*/
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/*
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* High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996
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*/
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.code32
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.text
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/segment.h>
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#include <asm/boot.h>
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#include <asm/msr.h>
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#include <asm/processor-flags.h>
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#include <asm/asm-offsets.h>
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#include <asm/bootparam.h>
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#include <asm/desc_defs.h>
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#include <asm/trapnr.h>
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#include "pgtable.h"
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/*
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* Fix alignment at 16 bytes. Following CONFIG_FUNCTION_ALIGNMENT will result
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* in assembly errors due to trying to move .org backward due to the excessive
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* alignment.
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*/
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#undef __ALIGN
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#define __ALIGN .balign 16, 0x90
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/*
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* Locally defined symbols should be marked hidden:
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*/
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.hidden _bss
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.hidden _ebss
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.hidden _end
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__HEAD
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/*
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* This macro gives the relative virtual address of X, i.e. the offset of X
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* from startup_32. This is the same as the link-time virtual address of X,
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* since startup_32 is at 0, but defining it this way tells the
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* assembler/linker that we do not want the actual run-time address of X. This
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* prevents the linker from trying to create unwanted run-time relocation
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* entries for the reference when the compressed kernel is linked as PIE.
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*
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* A reference X(%reg) will result in the link-time VA of X being stored with
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* the instruction, and a run-time R_X86_64_RELATIVE relocation entry that
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* adds the 64-bit base address where the kernel is loaded.
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*
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* Replacing it with (X-startup_32)(%reg) results in the offset being stored,
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* and no run-time relocation.
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*
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* The macro should be used as a displacement with a base register containing
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* the run-time address of startup_32 [i.e. rva(X)(%reg)], or as an immediate
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* [$ rva(X)].
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*
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* This macro can only be used from within the .head.text section, since the
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* expression requires startup_32 to be in the same section as the code being
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* assembled.
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*/
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#define rva(X) ((X) - startup_32)
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.code32
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SYM_FUNC_START(startup_32)
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/*
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* 32bit entry is 0 and it is ABI so immutable!
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* If we come here directly from a bootloader,
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* kernel(text+data+bss+brk) ramdisk, zero_page, command line
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* all need to be under the 4G limit.
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*/
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cld
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cli
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/*
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* Calculate the delta between where we were compiled to run
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* at and where we were actually loaded at. This can only be done
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* with a short local call on x86. Nothing else will tell us what
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* address we are running at. The reserved chunk of the real-mode
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* data at 0x1e4 (defined as a scratch field) are used as the stack
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* for this calculation. Only 4 bytes are needed.
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*/
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leal (BP_scratch+4)(%esi), %esp
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call 1f
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1: popl %ebp
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subl $ rva(1b), %ebp
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/* Load new GDT with the 64bit segments using 32bit descriptor */
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leal rva(gdt)(%ebp), %eax
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movl %eax, 2(%eax)
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lgdt (%eax)
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/* Load segment registers with our descriptors */
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movl $__BOOT_DS, %eax
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movl %eax, %ds
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movl %eax, %es
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movl %eax, %fs
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movl %eax, %gs
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movl %eax, %ss
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/* Setup a stack and load CS from current GDT */
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leal rva(boot_stack_end)(%ebp), %esp
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pushl $__KERNEL32_CS
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leal rva(1f)(%ebp), %eax
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pushl %eax
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lretl
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1:
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/* Setup Exception handling for SEV-ES */
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call startup32_load_idt
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/* Make sure cpu supports long mode. */
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call verify_cpu
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testl %eax, %eax
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jnz .Lno_longmode
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/*
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* Compute the delta between where we were compiled to run at
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* and where the code will actually run at.
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*
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* %ebp contains the address we are loaded at by the boot loader and %ebx
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* contains the address where we should move the kernel image temporarily
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* for safe in-place decompression.
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*/
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#ifdef CONFIG_RELOCATABLE
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movl %ebp, %ebx
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#ifdef CONFIG_EFI_STUB
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/*
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* If we were loaded via the EFI LoadImage service, startup_32 will be at an
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* offset to the start of the space allocated for the image. efi_pe_entry will
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* set up image_offset to tell us where the image actually starts, so that we
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* can use the full available buffer.
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* image_offset = startup_32 - image_base
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* Otherwise image_offset will be zero and has no effect on the calculations.
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*/
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subl rva(image_offset)(%ebp), %ebx
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#endif
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movl BP_kernel_alignment(%esi), %eax
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decl %eax
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addl %eax, %ebx
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notl %eax
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andl %eax, %ebx
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cmpl $LOAD_PHYSICAL_ADDR, %ebx
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jae 1f
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#endif
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movl $LOAD_PHYSICAL_ADDR, %ebx
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1:
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/* Target address to relocate to for decompression */
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addl BP_init_size(%esi), %ebx
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subl $ rva(_end), %ebx
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/*
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* Prepare for entering 64 bit mode
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*/
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/* Enable PAE mode */
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movl %cr4, %eax
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orl $X86_CR4_PAE, %eax
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movl %eax, %cr4
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/*
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* Build early 4G boot pagetable
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*/
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/*
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* If SEV is active then set the encryption mask in the page tables.
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* This will insure that when the kernel is copied and decompressed
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* it will be done so encrypted.
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*/
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call get_sev_encryption_bit
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xorl %edx, %edx
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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testl %eax, %eax
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jz 1f
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subl $32, %eax /* Encryption bit is always above bit 31 */
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bts %eax, %edx /* Set encryption mask for page tables */
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/*
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* Mark SEV as active in sev_status so that startup32_check_sev_cbit()
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* will do a check. The sev_status memory will be fully initialized
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* with the contents of MSR_AMD_SEV_STATUS later in
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* set_sev_encryption_mask(). For now it is sufficient to know that SEV
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* is active.
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*/
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movl $1, rva(sev_status)(%ebp)
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1:
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#endif
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/* Initialize Page tables to 0 */
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leal rva(pgtable)(%ebx), %edi
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xorl %eax, %eax
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movl $(BOOT_INIT_PGT_SIZE/4), %ecx
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rep stosl
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/* Build Level 4 */
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leal rva(pgtable + 0)(%ebx), %edi
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leal 0x1007 (%edi), %eax
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movl %eax, 0(%edi)
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addl %edx, 4(%edi)
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/* Build Level 3 */
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leal rva(pgtable + 0x1000)(%ebx), %edi
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leal 0x1007(%edi), %eax
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movl $4, %ecx
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1: movl %eax, 0x00(%edi)
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addl %edx, 0x04(%edi)
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addl $0x00001000, %eax
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addl $8, %edi
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decl %ecx
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jnz 1b
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/* Build Level 2 */
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leal rva(pgtable + 0x2000)(%ebx), %edi
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movl $0x00000183, %eax
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movl $2048, %ecx
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1: movl %eax, 0(%edi)
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addl %edx, 4(%edi)
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addl $0x00200000, %eax
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addl $8, %edi
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decl %ecx
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jnz 1b
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/* Enable the boot page tables */
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leal rva(pgtable)(%ebx), %eax
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movl %eax, %cr3
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/* Enable Long mode in EFER (Extended Feature Enable Register) */
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movl $MSR_EFER, %ecx
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rdmsr
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btsl $_EFER_LME, %eax
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wrmsr
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/* After gdt is loaded */
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xorl %eax, %eax
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lldt %ax
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movl $__BOOT_TSS, %eax
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ltr %ax
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/*
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* Setup for the jump to 64bit mode
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*
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* When the jump is performed we will be in long mode but
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* in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1
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* (and in turn EFER.LMA = 1). To jump into 64bit mode we use
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* the new gdt/idt that has __KERNEL_CS with CS.L = 1.
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* We place all of the values on our mini stack so lret can
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* used to perform that far jump.
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*/
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leal rva(startup_64)(%ebp), %eax
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#ifdef CONFIG_EFI_MIXED
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movl rva(efi32_boot_args)(%ebp), %edi
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testl %edi, %edi
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jz 1f
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leal rva(efi64_stub_entry)(%ebp), %eax
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movl rva(efi32_boot_args+4)(%ebp), %esi
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movl rva(efi32_boot_args+8)(%ebp), %edx // saved bootparams pointer
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testl %edx, %edx
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jnz 1f
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/*
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* efi_pe_entry uses MS calling convention, which requires 32 bytes of
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* shadow space on the stack even if all arguments are passed in
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* registers. We also need an additional 8 bytes for the space that
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* would be occupied by the return address, and this also results in
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* the correct stack alignment for entry.
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*/
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subl $40, %esp
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leal rva(efi_pe_entry)(%ebp), %eax
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movl %edi, %ecx // MS calling convention
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movl %esi, %edx
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1:
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#endif
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/* Check if the C-bit position is correct when SEV is active */
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call startup32_check_sev_cbit
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pushl $__KERNEL_CS
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pushl %eax
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/* Enter paged protected Mode, activating Long Mode */
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movl $(X86_CR0_PG | X86_CR0_PE), %eax /* Enable Paging and Protected mode */
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movl %eax, %cr0
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/* Jump from 32bit compatibility mode into 64bit mode. */
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lret
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SYM_FUNC_END(startup_32)
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#ifdef CONFIG_EFI_MIXED
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.org 0x190
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SYM_FUNC_START(efi32_stub_entry)
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add $0x4, %esp /* Discard return address */
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popl %ecx
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popl %edx
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popl %esi
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call 1f
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1: pop %ebp
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subl $ rva(1b), %ebp
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movl %esi, rva(efi32_boot_args+8)(%ebp)
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SYM_INNER_LABEL(efi32_pe_stub_entry, SYM_L_LOCAL)
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movl %ecx, rva(efi32_boot_args)(%ebp)
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movl %edx, rva(efi32_boot_args+4)(%ebp)
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movb $0, rva(efi_is64)(%ebp)
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/* Save firmware GDTR and code/data selectors */
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sgdtl rva(efi32_boot_gdt)(%ebp)
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movw %cs, rva(efi32_boot_cs)(%ebp)
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movw %ds, rva(efi32_boot_ds)(%ebp)
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/* Store firmware IDT descriptor */
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sidtl rva(efi32_boot_idt)(%ebp)
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/* Disable paging */
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movl %cr0, %eax
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btrl $X86_CR0_PG_BIT, %eax
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movl %eax, %cr0
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jmp startup_32
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SYM_FUNC_END(efi32_stub_entry)
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#endif
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.code64
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.org 0x200
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SYM_CODE_START(startup_64)
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/*
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* 64bit entry is 0x200 and it is ABI so immutable!
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* We come here either from startup_32 or directly from a
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* 64bit bootloader.
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* If we come here from a bootloader, kernel(text+data+bss+brk),
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* ramdisk, zero_page, command line could be above 4G.
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* We depend on an identity mapped page table being provided
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* that maps our entire kernel(text+data+bss+brk), zero page
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* and command line.
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*/
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cld
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cli
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/* Setup data segments. */
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xorl %eax, %eax
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movl %eax, %ds
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movl %eax, %es
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movl %eax, %ss
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movl %eax, %fs
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movl %eax, %gs
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/*
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* Compute the decompressed kernel start address. It is where
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|
|
* we were loaded at aligned to a 2M boundary. %rbp contains the
|
||
|
|
* decompressed kernel start address.
|
||
|
|
*
|
||
|
|
* If it is a relocatable kernel then decompress and run the kernel
|
||
|
|
* from load address aligned to 2MB addr, otherwise decompress and
|
||
|
|
* run the kernel from LOAD_PHYSICAL_ADDR
|
||
|
|
*
|
||
|
|
* We cannot rely on the calculation done in 32-bit mode, since we
|
||
|
|
* may have been invoked via the 64-bit entry point.
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Start with the delta to where the kernel will run at. */
|
||
|
|
#ifdef CONFIG_RELOCATABLE
|
||
|
|
leaq startup_32(%rip) /* - $startup_32 */, %rbp
|
||
|
|
|
||
|
|
#ifdef CONFIG_EFI_STUB
|
||
|
|
/*
|
||
|
|
* If we were loaded via the EFI LoadImage service, startup_32 will be at an
|
||
|
|
* offset to the start of the space allocated for the image. efi_pe_entry will
|
||
|
|
* set up image_offset to tell us where the image actually starts, so that we
|
||
|
|
* can use the full available buffer.
|
||
|
|
* image_offset = startup_32 - image_base
|
||
|
|
* Otherwise image_offset will be zero and has no effect on the calculations.
|
||
|
|
*/
|
||
|
|
movl image_offset(%rip), %eax
|
||
|
|
subq %rax, %rbp
|
||
|
|
#endif
|
||
|
|
|
||
|
|
movl BP_kernel_alignment(%rsi), %eax
|
||
|
|
decl %eax
|
||
|
|
addq %rax, %rbp
|
||
|
|
notq %rax
|
||
|
|
andq %rax, %rbp
|
||
|
|
cmpq $LOAD_PHYSICAL_ADDR, %rbp
|
||
|
|
jae 1f
|
||
|
|
#endif
|
||
|
|
movq $LOAD_PHYSICAL_ADDR, %rbp
|
||
|
|
1:
|
||
|
|
|
||
|
|
/* Target address to relocate to for decompression */
|
||
|
|
movl BP_init_size(%rsi), %ebx
|
||
|
|
subl $ rva(_end), %ebx
|
||
|
|
addq %rbp, %rbx
|
||
|
|
|
||
|
|
/* Set up the stack */
|
||
|
|
leaq rva(boot_stack_end)(%rbx), %rsp
|
||
|
|
|
||
|
|
/*
|
||
|
|
* At this point we are in long mode with 4-level paging enabled,
|
||
|
|
* but we might want to enable 5-level paging or vice versa.
|
||
|
|
*
|
||
|
|
* The problem is that we cannot do it directly. Setting or clearing
|
||
|
|
* CR4.LA57 in long mode would trigger #GP. So we need to switch off
|
||
|
|
* long mode and paging first.
|
||
|
|
*
|
||
|
|
* We also need a trampoline in lower memory to switch over from
|
||
|
|
* 4- to 5-level paging for cases when the bootloader puts the kernel
|
||
|
|
* above 4G, but didn't enable 5-level paging for us.
|
||
|
|
*
|
||
|
|
* The same trampoline can be used to switch from 5- to 4-level paging
|
||
|
|
* mode, like when starting 4-level paging kernel via kexec() when
|
||
|
|
* original kernel worked in 5-level paging mode.
|
||
|
|
*
|
||
|
|
* For the trampoline, we need the top page table to reside in lower
|
||
|
|
* memory as we don't have a way to load 64-bit values into CR3 in
|
||
|
|
* 32-bit mode.
|
||
|
|
*
|
||
|
|
* We go though the trampoline even if we don't have to: if we're
|
||
|
|
* already in a desired paging mode. This way the trampoline code gets
|
||
|
|
* tested on every boot.
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Make sure we have GDT with 32-bit code segment */
|
||
|
|
leaq gdt64(%rip), %rax
|
||
|
|
addq %rax, 2(%rax)
|
||
|
|
lgdt (%rax)
|
||
|
|
|
||
|
|
/* Reload CS so IRET returns to a CS actually in the GDT */
|
||
|
|
pushq $__KERNEL_CS
|
||
|
|
leaq .Lon_kernel_cs(%rip), %rax
|
||
|
|
pushq %rax
|
||
|
|
lretq
|
||
|
|
|
||
|
|
.Lon_kernel_cs:
|
||
|
|
|
||
|
|
pushq %rsi
|
||
|
|
call load_stage1_idt
|
||
|
|
popq %rsi
|
||
|
|
|
||
|
|
/*
|
||
|
|
* paging_prepare() sets up the trampoline and checks if we need to
|
||
|
|
* enable 5-level paging.
|
||
|
|
*
|
||
|
|
* paging_prepare() returns a two-quadword structure which lands
|
||
|
|
* into RDX:RAX:
|
||
|
|
* - Address of the trampoline is returned in RAX.
|
||
|
|
* - Non zero RDX means trampoline needs to enable 5-level
|
||
|
|
* paging.
|
||
|
|
*
|
||
|
|
* RSI holds real mode data and needs to be preserved across
|
||
|
|
* this function call.
|
||
|
|
*/
|
||
|
|
pushq %rsi
|
||
|
|
movq %rsi, %rdi /* real mode address */
|
||
|
|
call paging_prepare
|
||
|
|
popq %rsi
|
||
|
|
|
||
|
|
/* Save the trampoline address in RCX */
|
||
|
|
movq %rax, %rcx
|
||
|
|
|
||
|
|
/* Set up 32-bit addressable stack */
|
||
|
|
leaq TRAMPOLINE_32BIT_STACK_END(%rcx), %rsp
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Preserve live 64-bit registers on the stack: this is necessary
|
||
|
|
* because the architecture does not guarantee that GPRs will retain
|
||
|
|
* their full 64-bit values across a 32-bit mode switch.
|
||
|
|
*/
|
||
|
|
pushq %rbp
|
||
|
|
pushq %rbx
|
||
|
|
pushq %rsi
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Push the 64-bit address of trampoline_return() onto the new stack.
|
||
|
|
* It will be used by the trampoline to return to the main code. Due to
|
||
|
|
* the 32-bit mode switch, it cannot be kept it in a register either.
|
||
|
|
*/
|
||
|
|
leaq trampoline_return(%rip), %rdi
|
||
|
|
pushq %rdi
|
||
|
|
|
||
|
|
/* Switch to compatibility mode (CS.L = 0 CS.D = 1) via far return */
|
||
|
|
pushq $__KERNEL32_CS
|
||
|
|
leaq TRAMPOLINE_32BIT_CODE_OFFSET(%rax), %rax
|
||
|
|
pushq %rax
|
||
|
|
lretq
|
||
|
|
trampoline_return:
|
||
|
|
/* Restore live 64-bit registers */
|
||
|
|
popq %rsi
|
||
|
|
popq %rbx
|
||
|
|
popq %rbp
|
||
|
|
|
||
|
|
/* Restore the stack, the 32-bit trampoline uses its own stack */
|
||
|
|
leaq rva(boot_stack_end)(%rbx), %rsp
|
||
|
|
|
||
|
|
/*
|
||
|
|
* cleanup_trampoline() would restore trampoline memory.
|
||
|
|
*
|
||
|
|
* RDI is address of the page table to use instead of page table
|
||
|
|
* in trampoline memory (if required).
|
||
|
|
*
|
||
|
|
* RSI holds real mode data and needs to be preserved across
|
||
|
|
* this function call.
|
||
|
|
*/
|
||
|
|
pushq %rsi
|
||
|
|
leaq rva(top_pgtable)(%rbx), %rdi
|
||
|
|
call cleanup_trampoline
|
||
|
|
popq %rsi
|
||
|
|
|
||
|
|
/* Zero EFLAGS */
|
||
|
|
pushq $0
|
||
|
|
popfq
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Copy the compressed kernel to the end of our buffer
|
||
|
|
* where decompression in place becomes safe.
|
||
|
|
*/
|
||
|
|
pushq %rsi
|
||
|
|
leaq (_bss-8)(%rip), %rsi
|
||
|
|
leaq rva(_bss-8)(%rbx), %rdi
|
||
|
|
movl $(_bss - startup_32), %ecx
|
||
|
|
shrl $3, %ecx
|
||
|
|
std
|
||
|
|
rep movsq
|
||
|
|
cld
|
||
|
|
popq %rsi
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The GDT may get overwritten either during the copy we just did or
|
||
|
|
* during extract_kernel below. To avoid any issues, repoint the GDTR
|
||
|
|
* to the new copy of the GDT.
|
||
|
|
*/
|
||
|
|
leaq rva(gdt64)(%rbx), %rax
|
||
|
|
leaq rva(gdt)(%rbx), %rdx
|
||
|
|
movq %rdx, 2(%rax)
|
||
|
|
lgdt (%rax)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Jump to the relocated address.
|
||
|
|
*/
|
||
|
|
leaq rva(.Lrelocated)(%rbx), %rax
|
||
|
|
jmp *%rax
|
||
|
|
SYM_CODE_END(startup_64)
|
||
|
|
|
||
|
|
#ifdef CONFIG_EFI_STUB
|
||
|
|
.org 0x390
|
||
|
|
SYM_FUNC_START(efi64_stub_entry)
|
||
|
|
SYM_FUNC_START_ALIAS(efi_stub_entry)
|
||
|
|
and $~0xf, %rsp /* realign the stack */
|
||
|
|
movq %rdx, %rbx /* save boot_params pointer */
|
||
|
|
call efi_main
|
||
|
|
movq %rbx,%rsi
|
||
|
|
leaq rva(startup_64)(%rax), %rax
|
||
|
|
jmp *%rax
|
||
|
|
SYM_FUNC_END(efi64_stub_entry)
|
||
|
|
SYM_FUNC_END_ALIAS(efi_stub_entry)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
.text
|
||
|
|
SYM_FUNC_START_LOCAL_NOALIGN(.Lrelocated)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Clear BSS (stack is currently empty)
|
||
|
|
*/
|
||
|
|
xorl %eax, %eax
|
||
|
|
leaq _bss(%rip), %rdi
|
||
|
|
leaq _ebss(%rip), %rcx
|
||
|
|
subq %rdi, %rcx
|
||
|
|
shrq $3, %rcx
|
||
|
|
rep stosq
|
||
|
|
|
||
|
|
/*
|
||
|
|
* If running as an SEV guest, the encryption mask is required in the
|
||
|
|
* page-table setup code below. When the guest also has SEV-ES enabled
|
||
|
|
* set_sev_encryption_mask() will cause #VC exceptions, but the stage2
|
||
|
|
* handler can't map its GHCB because the page-table is not set up yet.
|
||
|
|
* So set up the encryption mask here while still on the stage1 #VC
|
||
|
|
* handler. Then load stage2 IDT and switch to the kernel's own
|
||
|
|
* page-table.
|
||
|
|
*/
|
||
|
|
pushq %rsi
|
||
|
|
call set_sev_encryption_mask
|
||
|
|
call load_stage2_idt
|
||
|
|
|
||
|
|
/* Pass boot_params to initialize_identity_maps() */
|
||
|
|
movq (%rsp), %rdi
|
||
|
|
call initialize_identity_maps
|
||
|
|
popq %rsi
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Do the extraction, and jump to the new kernel..
|
||
|
|
*/
|
||
|
|
pushq %rsi /* Save the real mode argument */
|
||
|
|
movq %rsi, %rdi /* real mode address */
|
||
|
|
leaq boot_heap(%rip), %rsi /* malloc area for uncompression */
|
||
|
|
leaq input_data(%rip), %rdx /* input_data */
|
||
|
|
movl input_len(%rip), %ecx /* input_len */
|
||
|
|
movq %rbp, %r8 /* output target address */
|
||
|
|
movl output_len(%rip), %r9d /* decompressed length, end of relocs */
|
||
|
|
call extract_kernel /* returns kernel location in %rax */
|
||
|
|
popq %rsi
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Jump to the decompressed kernel.
|
||
|
|
*/
|
||
|
|
jmp *%rax
|
||
|
|
SYM_FUNC_END(.Lrelocated)
|
||
|
|
|
||
|
|
.code32
|
||
|
|
/*
|
||
|
|
* This is the 32-bit trampoline that will be copied over to low memory.
|
||
|
|
*
|
||
|
|
* Return address is at the top of the stack (might be above 4G).
|
||
|
|
* ECX contains the base address of the trampoline memory.
|
||
|
|
* Non zero RDX means trampoline needs to enable 5-level paging.
|
||
|
|
*/
|
||
|
|
SYM_CODE_START(trampoline_32bit_src)
|
||
|
|
/* Set up data and stack segments */
|
||
|
|
movl $__KERNEL_DS, %eax
|
||
|
|
movl %eax, %ds
|
||
|
|
movl %eax, %ss
|
||
|
|
|
||
|
|
/* Disable paging */
|
||
|
|
movl %cr0, %eax
|
||
|
|
btrl $X86_CR0_PG_BIT, %eax
|
||
|
|
movl %eax, %cr0
|
||
|
|
|
||
|
|
/* Check what paging mode we want to be in after the trampoline */
|
||
|
|
testl %edx, %edx
|
||
|
|
jz 1f
|
||
|
|
|
||
|
|
/* We want 5-level paging: don't touch CR3 if it already points to 5-level page tables */
|
||
|
|
movl %cr4, %eax
|
||
|
|
testl $X86_CR4_LA57, %eax
|
||
|
|
jnz 3f
|
||
|
|
jmp 2f
|
||
|
|
1:
|
||
|
|
/* We want 4-level paging: don't touch CR3 if it already points to 4-level page tables */
|
||
|
|
movl %cr4, %eax
|
||
|
|
testl $X86_CR4_LA57, %eax
|
||
|
|
jz 3f
|
||
|
|
2:
|
||
|
|
/* Point CR3 to the trampoline's new top level page table */
|
||
|
|
leal TRAMPOLINE_32BIT_PGTABLE_OFFSET(%ecx), %eax
|
||
|
|
movl %eax, %cr3
|
||
|
|
3:
|
||
|
|
/* Set EFER.LME=1 as a precaution in case hypervsior pulls the rug */
|
||
|
|
pushl %ecx
|
||
|
|
pushl %edx
|
||
|
|
movl $MSR_EFER, %ecx
|
||
|
|
rdmsr
|
||
|
|
btsl $_EFER_LME, %eax
|
||
|
|
wrmsr
|
||
|
|
popl %edx
|
||
|
|
popl %ecx
|
||
|
|
|
||
|
|
/* Enable PAE and LA57 (if required) paging modes */
|
||
|
|
movl $X86_CR4_PAE, %eax
|
||
|
|
testl %edx, %edx
|
||
|
|
jz 1f
|
||
|
|
orl $X86_CR4_LA57, %eax
|
||
|
|
1:
|
||
|
|
movl %eax, %cr4
|
||
|
|
|
||
|
|
/* Calculate address of paging_enabled() once we are executing in the trampoline */
|
||
|
|
leal .Lpaging_enabled - trampoline_32bit_src + TRAMPOLINE_32BIT_CODE_OFFSET(%ecx), %eax
|
||
|
|
|
||
|
|
/* Prepare the stack for far return to Long Mode */
|
||
|
|
pushl $__KERNEL_CS
|
||
|
|
pushl %eax
|
||
|
|
|
||
|
|
/* Enable paging again */
|
||
|
|
movl $(X86_CR0_PG | X86_CR0_PE), %eax
|
||
|
|
movl %eax, %cr0
|
||
|
|
|
||
|
|
lret
|
||
|
|
SYM_CODE_END(trampoline_32bit_src)
|
||
|
|
|
||
|
|
.code64
|
||
|
|
SYM_FUNC_START_LOCAL_NOALIGN(.Lpaging_enabled)
|
||
|
|
/* Return from the trampoline */
|
||
|
|
retq
|
||
|
|
SYM_FUNC_END(.Lpaging_enabled)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The trampoline code has a size limit.
|
||
|
|
* Make sure we fail to compile if the trampoline code grows
|
||
|
|
* beyond TRAMPOLINE_32BIT_CODE_SIZE bytes.
|
||
|
|
*/
|
||
|
|
.org trampoline_32bit_src + TRAMPOLINE_32BIT_CODE_SIZE
|
||
|
|
|
||
|
|
.code32
|
||
|
|
SYM_FUNC_START_LOCAL_NOALIGN(.Lno_longmode)
|
||
|
|
/* This isn't an x86-64 CPU, so hang intentionally, we cannot continue */
|
||
|
|
1:
|
||
|
|
hlt
|
||
|
|
jmp 1b
|
||
|
|
SYM_FUNC_END(.Lno_longmode)
|
||
|
|
|
||
|
|
#include "../../kernel/verify_cpu.S"
|
||
|
|
|
||
|
|
.data
|
||
|
|
SYM_DATA_START_LOCAL(gdt64)
|
||
|
|
.word gdt_end - gdt - 1
|
||
|
|
.quad gdt - gdt64
|
||
|
|
SYM_DATA_END(gdt64)
|
||
|
|
.balign 8
|
||
|
|
SYM_DATA_START_LOCAL(gdt)
|
||
|
|
.word gdt_end - gdt - 1
|
||
|
|
.long 0
|
||
|
|
.word 0
|
||
|
|
.quad 0x00cf9a000000ffff /* __KERNEL32_CS */
|
||
|
|
.quad 0x00af9a000000ffff /* __KERNEL_CS */
|
||
|
|
.quad 0x00cf92000000ffff /* __KERNEL_DS */
|
||
|
|
.quad 0x0080890000000000 /* TS descriptor */
|
||
|
|
.quad 0x0000000000000000 /* TS continued */
|
||
|
|
SYM_DATA_END_LABEL(gdt, SYM_L_LOCAL, gdt_end)
|
||
|
|
|
||
|
|
SYM_DATA_START(boot_idt_desc)
|
||
|
|
.word boot_idt_end - boot_idt - 1
|
||
|
|
.quad 0
|
||
|
|
SYM_DATA_END(boot_idt_desc)
|
||
|
|
.balign 8
|
||
|
|
SYM_DATA_START(boot_idt)
|
||
|
|
.rept BOOT_IDT_ENTRIES
|
||
|
|
.quad 0
|
||
|
|
.quad 0
|
||
|
|
.endr
|
||
|
|
SYM_DATA_END_LABEL(boot_idt, SYM_L_GLOBAL, boot_idt_end)
|
||
|
|
|
||
|
|
#ifdef CONFIG_AMD_MEM_ENCRYPT
|
||
|
|
SYM_DATA_START(boot32_idt_desc)
|
||
|
|
.word boot32_idt_end - boot32_idt - 1
|
||
|
|
.long 0
|
||
|
|
SYM_DATA_END(boot32_idt_desc)
|
||
|
|
.balign 8
|
||
|
|
SYM_DATA_START(boot32_idt)
|
||
|
|
.rept 32
|
||
|
|
.quad 0
|
||
|
|
.endr
|
||
|
|
SYM_DATA_END_LABEL(boot32_idt, SYM_L_GLOBAL, boot32_idt_end)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_EFI_STUB
|
||
|
|
SYM_DATA(image_offset, .long 0)
|
||
|
|
#endif
|
||
|
|
#ifdef CONFIG_EFI_MIXED
|
||
|
|
SYM_DATA_LOCAL(efi32_boot_args, .long 0, 0, 0)
|
||
|
|
SYM_DATA(efi_is64, .byte 1)
|
||
|
|
|
||
|
|
#define ST32_boottime 60 // offsetof(efi_system_table_32_t, boottime)
|
||
|
|
#define BS32_handle_protocol 88 // offsetof(efi_boot_services_32_t, handle_protocol)
|
||
|
|
#define LI32_image_base 32 // offsetof(efi_loaded_image_32_t, image_base)
|
||
|
|
|
||
|
|
__HEAD
|
||
|
|
.code32
|
||
|
|
SYM_FUNC_START(efi32_pe_entry)
|
||
|
|
/*
|
||
|
|
* efi_status_t efi32_pe_entry(efi_handle_t image_handle,
|
||
|
|
* efi_system_table_32_t *sys_table)
|
||
|
|
*/
|
||
|
|
|
||
|
|
pushl %ebp
|
||
|
|
movl %esp, %ebp
|
||
|
|
pushl %eax // dummy push to allocate loaded_image
|
||
|
|
|
||
|
|
pushl %ebx // save callee-save registers
|
||
|
|
pushl %edi
|
||
|
|
|
||
|
|
call verify_cpu // check for long mode support
|
||
|
|
testl %eax, %eax
|
||
|
|
movl $0x80000003, %eax // EFI_UNSUPPORTED
|
||
|
|
jnz 2f
|
||
|
|
|
||
|
|
call 1f
|
||
|
|
1: pop %ebx
|
||
|
|
subl $ rva(1b), %ebx
|
||
|
|
|
||
|
|
/* Get the loaded image protocol pointer from the image handle */
|
||
|
|
leal -4(%ebp), %eax
|
||
|
|
pushl %eax // &loaded_image
|
||
|
|
leal rva(loaded_image_proto)(%ebx), %eax
|
||
|
|
pushl %eax // pass the GUID address
|
||
|
|
pushl 8(%ebp) // pass the image handle
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Note the alignment of the stack frame.
|
||
|
|
* sys_table
|
||
|
|
* handle <-- 16-byte aligned on entry by ABI
|
||
|
|
* return address
|
||
|
|
* frame pointer
|
||
|
|
* loaded_image <-- local variable
|
||
|
|
* saved %ebx <-- 16-byte aligned here
|
||
|
|
* saved %edi
|
||
|
|
* &loaded_image
|
||
|
|
* &loaded_image_proto
|
||
|
|
* handle <-- 16-byte aligned for call to handle_protocol
|
||
|
|
*/
|
||
|
|
|
||
|
|
movl 12(%ebp), %eax // sys_table
|
||
|
|
movl ST32_boottime(%eax), %eax // sys_table->boottime
|
||
|
|
call *BS32_handle_protocol(%eax) // sys_table->boottime->handle_protocol
|
||
|
|
addl $12, %esp // restore argument space
|
||
|
|
testl %eax, %eax
|
||
|
|
jnz 2f
|
||
|
|
|
||
|
|
movl 8(%ebp), %ecx // image_handle
|
||
|
|
movl 12(%ebp), %edx // sys_table
|
||
|
|
movl -4(%ebp), %esi // loaded_image
|
||
|
|
movl LI32_image_base(%esi), %esi // loaded_image->image_base
|
||
|
|
movl %ebx, %ebp // startup_32 for efi32_pe_stub_entry
|
||
|
|
/*
|
||
|
|
* We need to set the image_offset variable here since startup_32() will
|
||
|
|
* use it before we get to the 64-bit efi_pe_entry() in C code.
|
||
|
|
*/
|
||
|
|
subl %esi, %ebx
|
||
|
|
movl %ebx, rva(image_offset)(%ebp) // save image_offset
|
||
|
|
jmp efi32_pe_stub_entry
|
||
|
|
|
||
|
|
2: popl %edi // restore callee-save registers
|
||
|
|
popl %ebx
|
||
|
|
leave
|
||
|
|
RET
|
||
|
|
SYM_FUNC_END(efi32_pe_entry)
|
||
|
|
|
||
|
|
.section ".rodata"
|
||
|
|
/* EFI loaded image protocol GUID */
|
||
|
|
.balign 4
|
||
|
|
SYM_DATA_START_LOCAL(loaded_image_proto)
|
||
|
|
.long 0x5b1b31a1
|
||
|
|
.word 0x9562, 0x11d2
|
||
|
|
.byte 0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b
|
||
|
|
SYM_DATA_END(loaded_image_proto)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_AMD_MEM_ENCRYPT
|
||
|
|
__HEAD
|
||
|
|
.code32
|
||
|
|
/*
|
||
|
|
* Write an IDT entry into boot32_idt
|
||
|
|
*
|
||
|
|
* Parameters:
|
||
|
|
*
|
||
|
|
* %eax: Handler address
|
||
|
|
* %edx: Vector number
|
||
|
|
*
|
||
|
|
* Physical offset is expected in %ebp
|
||
|
|
*/
|
||
|
|
SYM_FUNC_START(startup32_set_idt_entry)
|
||
|
|
push %ebx
|
||
|
|
push %ecx
|
||
|
|
|
||
|
|
/* IDT entry address to %ebx */
|
||
|
|
leal rva(boot32_idt)(%ebp), %ebx
|
||
|
|
shl $3, %edx
|
||
|
|
addl %edx, %ebx
|
||
|
|
|
||
|
|
/* Build IDT entry, lower 4 bytes */
|
||
|
|
movl %eax, %edx
|
||
|
|
andl $0x0000ffff, %edx # Target code segment offset [15:0]
|
||
|
|
movl $__KERNEL32_CS, %ecx # Target code segment selector
|
||
|
|
shl $16, %ecx
|
||
|
|
orl %ecx, %edx
|
||
|
|
|
||
|
|
/* Store lower 4 bytes to IDT */
|
||
|
|
movl %edx, (%ebx)
|
||
|
|
|
||
|
|
/* Build IDT entry, upper 4 bytes */
|
||
|
|
movl %eax, %edx
|
||
|
|
andl $0xffff0000, %edx # Target code segment offset [31:16]
|
||
|
|
orl $0x00008e00, %edx # Present, Type 32-bit Interrupt Gate
|
||
|
|
|
||
|
|
/* Store upper 4 bytes to IDT */
|
||
|
|
movl %edx, 4(%ebx)
|
||
|
|
|
||
|
|
pop %ecx
|
||
|
|
pop %ebx
|
||
|
|
RET
|
||
|
|
SYM_FUNC_END(startup32_set_idt_entry)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
SYM_FUNC_START(startup32_load_idt)
|
||
|
|
#ifdef CONFIG_AMD_MEM_ENCRYPT
|
||
|
|
/* #VC handler */
|
||
|
|
leal rva(startup32_vc_handler)(%ebp), %eax
|
||
|
|
movl $X86_TRAP_VC, %edx
|
||
|
|
call startup32_set_idt_entry
|
||
|
|
|
||
|
|
/* Load IDT */
|
||
|
|
leal rva(boot32_idt)(%ebp), %eax
|
||
|
|
movl %eax, rva(boot32_idt_desc+2)(%ebp)
|
||
|
|
lidt rva(boot32_idt_desc)(%ebp)
|
||
|
|
#endif
|
||
|
|
RET
|
||
|
|
SYM_FUNC_END(startup32_load_idt)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Check for the correct C-bit position when the startup_32 boot-path is used.
|
||
|
|
*
|
||
|
|
* The check makes use of the fact that all memory is encrypted when paging is
|
||
|
|
* disabled. The function creates 64 bits of random data using the RDRAND
|
||
|
|
* instruction. RDRAND is mandatory for SEV guests, so always available. If the
|
||
|
|
* hypervisor violates that the kernel will crash right here.
|
||
|
|
*
|
||
|
|
* The 64 bits of random data are stored to a memory location and at the same
|
||
|
|
* time kept in the %eax and %ebx registers. Since encryption is always active
|
||
|
|
* when paging is off the random data will be stored encrypted in main memory.
|
||
|
|
*
|
||
|
|
* Then paging is enabled. When the C-bit position is correct all memory is
|
||
|
|
* still mapped encrypted and comparing the register values with memory will
|
||
|
|
* succeed. An incorrect C-bit position will map all memory unencrypted, so that
|
||
|
|
* the compare will use the encrypted random data and fail.
|
||
|
|
*/
|
||
|
|
SYM_FUNC_START(startup32_check_sev_cbit)
|
||
|
|
#ifdef CONFIG_AMD_MEM_ENCRYPT
|
||
|
|
pushl %eax
|
||
|
|
pushl %ebx
|
||
|
|
pushl %ecx
|
||
|
|
pushl %edx
|
||
|
|
|
||
|
|
/* Check for non-zero sev_status */
|
||
|
|
movl rva(sev_status)(%ebp), %eax
|
||
|
|
testl %eax, %eax
|
||
|
|
jz 4f
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Get two 32-bit random values - Don't bail out if RDRAND fails
|
||
|
|
* because it is better to prevent forward progress if no random value
|
||
|
|
* can be gathered.
|
||
|
|
*/
|
||
|
|
1: rdrand %eax
|
||
|
|
jnc 1b
|
||
|
|
2: rdrand %ebx
|
||
|
|
jnc 2b
|
||
|
|
|
||
|
|
/* Store to memory and keep it in the registers */
|
||
|
|
movl %eax, rva(sev_check_data)(%ebp)
|
||
|
|
movl %ebx, rva(sev_check_data+4)(%ebp)
|
||
|
|
|
||
|
|
/* Enable paging to see if encryption is active */
|
||
|
|
movl %cr0, %edx /* Backup %cr0 in %edx */
|
||
|
|
movl $(X86_CR0_PG | X86_CR0_PE), %ecx /* Enable Paging and Protected mode */
|
||
|
|
movl %ecx, %cr0
|
||
|
|
|
||
|
|
cmpl %eax, rva(sev_check_data)(%ebp)
|
||
|
|
jne 3f
|
||
|
|
cmpl %ebx, rva(sev_check_data+4)(%ebp)
|
||
|
|
jne 3f
|
||
|
|
|
||
|
|
movl %edx, %cr0 /* Restore previous %cr0 */
|
||
|
|
|
||
|
|
jmp 4f
|
||
|
|
|
||
|
|
3: /* Check failed - hlt the machine */
|
||
|
|
hlt
|
||
|
|
jmp 3b
|
||
|
|
|
||
|
|
4:
|
||
|
|
popl %edx
|
||
|
|
popl %ecx
|
||
|
|
popl %ebx
|
||
|
|
popl %eax
|
||
|
|
#endif
|
||
|
|
RET
|
||
|
|
SYM_FUNC_END(startup32_check_sev_cbit)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Stack and heap for uncompression
|
||
|
|
*/
|
||
|
|
.bss
|
||
|
|
.balign 4
|
||
|
|
SYM_DATA_LOCAL(boot_heap, .fill BOOT_HEAP_SIZE, 1, 0)
|
||
|
|
|
||
|
|
SYM_DATA_START_LOCAL(boot_stack)
|
||
|
|
.fill BOOT_STACK_SIZE, 1, 0
|
||
|
|
.balign 16
|
||
|
|
SYM_DATA_END_LABEL(boot_stack, SYM_L_LOCAL, boot_stack_end)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Space for page tables (not in .bss so not zeroed)
|
||
|
|
*/
|
||
|
|
.section ".pgtable","aw",@nobits
|
||
|
|
.balign 4096
|
||
|
|
SYM_DATA_LOCAL(pgtable, .fill BOOT_PGT_SIZE, 1, 0)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The page table is going to be used instead of page table in the trampoline
|
||
|
|
* memory.
|
||
|
|
*/
|
||
|
|
SYM_DATA_LOCAL(top_pgtable, .fill PAGE_SIZE, 1, 0)
|