378 lines
11 KiB
C
378 lines
11 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2005-2017 Andes Technology Corporation
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#ifndef _ASMNDS32_PGTABLE_H
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#define _ASMNDS32_PGTABLE_H
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#include <asm-generic/pgtable-nopmd.h>
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#include <linux/sizes.h>
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#include <asm/memory.h>
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#include <asm/nds32.h>
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#ifndef __ASSEMBLY__
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#include <asm/fixmap.h>
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#include <nds32_intrinsic.h>
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#endif
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#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
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#define PGDIR_SHIFT 22
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#define PTRS_PER_PGD 1024
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#define PTRS_PER_PTE 1024
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#endif
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#ifdef CONFIG_ANDES_PAGE_SIZE_8KB
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#define PGDIR_SHIFT 24
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#define PTRS_PER_PGD 256
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#define PTRS_PER_PTE 2048
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#endif
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#ifndef __ASSEMBLY__
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extern void __pte_error(const char *file, int line, unsigned long val);
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extern void __pgd_error(const char *file, int line, unsigned long val);
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#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
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#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
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#endif /* !__ASSEMBLY__ */
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* This is the lowest virtual address we can permit any user space
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* mapping to be mapped at. This is particularly important for
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* non-high vector CPUs.
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*/
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#define FIRST_USER_ADDRESS 0x8000
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#ifdef CONFIG_HIGHMEM
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#define CONSISTENT_BASE ((PKMAP_BASE) - (SZ_2M))
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#define CONSISTENT_END (PKMAP_BASE)
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#else
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#define CONSISTENT_BASE (FIXADDR_START - SZ_2M)
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#define CONSISTENT_END (FIXADDR_START)
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#endif
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#define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
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#ifdef CONFIG_HIGHMEM
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#ifndef __ASSEMBLY__
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#include <asm/highmem.h>
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#endif
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#endif
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#define VMALLOC_RESERVE SZ_128M
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#define VMALLOC_END (CONSISTENT_BASE - PAGE_SIZE)
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#define VMALLOC_START ((VMALLOC_END) - VMALLOC_RESERVE)
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#define VMALLOC_VMADDR(x) ((unsigned long)(x))
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#define MAXMEM __pa(VMALLOC_START)
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#define MAXMEM_PFN PFN_DOWN(MAXMEM)
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#define FIRST_USER_PGD_NR 0
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#define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) + FIRST_USER_PGD_NR)
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/* L2 PTE */
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#define _PAGE_V (1UL << 0)
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#define _PAGE_M_XKRW (0UL << 1)
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#define _PAGE_M_UR_KR (1UL << 1)
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#define _PAGE_M_UR_KRW (2UL << 1)
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#define _PAGE_M_URW_KRW (3UL << 1)
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#define _PAGE_M_KR (5UL << 1)
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#define _PAGE_M_KRW (7UL << 1)
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#define _PAGE_D (1UL << 4)
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#define _PAGE_E (1UL << 5)
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#define _PAGE_A (1UL << 6)
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#define _PAGE_G (1UL << 7)
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#define _PAGE_C_DEV (0UL << 8)
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#define _PAGE_C_DEV_WB (1UL << 8)
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#define _PAGE_C_MEM (2UL << 8)
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#define _PAGE_C_MEM_SHRD_WB (4UL << 8)
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#define _PAGE_C_MEM_SHRD_WT (5UL << 8)
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#define _PAGE_C_MEM_WB (6UL << 8)
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#define _PAGE_C_MEM_WT (7UL << 8)
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#define _PAGE_L (1UL << 11)
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#define _HAVE_PAGE_L (_PAGE_L)
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#define _PAGE_FILE (1UL << 1)
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#define _PAGE_YOUNG 0
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#define _PAGE_M_MASK _PAGE_M_KRW
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#define _PAGE_C_MASK _PAGE_C_MEM_WT
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#ifdef CONFIG_SMP
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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#define _PAGE_CACHE_SHRD _PAGE_C_MEM_SHRD_WT
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#else
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#define _PAGE_CACHE_SHRD _PAGE_C_MEM_SHRD_WB
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#endif
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#else
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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#define _PAGE_CACHE_SHRD _PAGE_C_MEM_WT
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#else
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#define _PAGE_CACHE_SHRD _PAGE_C_MEM_WB
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#endif
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#endif
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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#define _PAGE_CACHE _PAGE_C_MEM_WT
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#else
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#define _PAGE_CACHE _PAGE_C_MEM_WB
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#endif
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#define _PAGE_IOREMAP \
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(_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_G | _PAGE_C_DEV)
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/*
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* + Level 1 descriptor (PMD)
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*/
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#define PMD_TYPE_TABLE 0
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#ifndef __ASSEMBLY__
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#define _PAGE_USER_TABLE PMD_TYPE_TABLE
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#define _PAGE_KERNEL_TABLE PMD_TYPE_TABLE
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#define PAGE_EXEC __pgprot(_PAGE_V | _PAGE_M_XKRW | _PAGE_E)
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#define PAGE_NONE __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_A)
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#define PAGE_READ __pgprot(_PAGE_V | _PAGE_M_UR_KR)
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#define PAGE_RDWR __pgprot(_PAGE_V | _PAGE_M_URW_KRW | _PAGE_D)
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#define PAGE_COPY __pgprot(_PAGE_V | _PAGE_M_UR_KR)
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#define PAGE_UXKRWX_V1 __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
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#define PAGE_UXKRWX_V2 __pgprot(_PAGE_V | _PAGE_M_XKRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
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#define PAGE_URXKRWX_V2 __pgprot(_PAGE_V | _PAGE_M_UR_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
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#define PAGE_CACHE_L1 __pgprot(_HAVE_PAGE_L | _PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE)
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#define PAGE_MEMORY __pgprot(_HAVE_PAGE_L | _PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
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#define PAGE_KERNEL __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
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#define PAGE_SHARED __pgprot(_PAGE_V | _PAGE_M_URW_KRW | _PAGE_D | _PAGE_CACHE_SHRD)
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#define PAGE_DEVICE __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_G | _PAGE_C_DEV)
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#endif /* __ASSEMBLY__ */
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/* xwr */
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#define __P000 (PAGE_NONE | _PAGE_CACHE_SHRD)
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#define __P001 (PAGE_READ | _PAGE_CACHE_SHRD)
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#define __P010 (PAGE_COPY | _PAGE_CACHE_SHRD)
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#define __P011 (PAGE_COPY | _PAGE_CACHE_SHRD)
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#define __P100 (PAGE_EXEC | _PAGE_CACHE_SHRD)
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#define __P101 (PAGE_READ | _PAGE_E | _PAGE_CACHE_SHRD)
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#define __P110 (PAGE_COPY | _PAGE_E | _PAGE_CACHE_SHRD)
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#define __P111 (PAGE_COPY | _PAGE_E | _PAGE_CACHE_SHRD)
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#define __S000 (PAGE_NONE | _PAGE_CACHE_SHRD)
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#define __S001 (PAGE_READ | _PAGE_CACHE_SHRD)
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#define __S010 (PAGE_RDWR | _PAGE_CACHE_SHRD)
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#define __S011 (PAGE_RDWR | _PAGE_CACHE_SHRD)
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#define __S100 (PAGE_EXEC | _PAGE_CACHE_SHRD)
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#define __S101 (PAGE_READ | _PAGE_E | _PAGE_CACHE_SHRD)
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#define __S110 (PAGE_RDWR | _PAGE_E | _PAGE_CACHE_SHRD)
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#define __S111 (PAGE_RDWR | _PAGE_E | _PAGE_CACHE_SHRD)
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#ifndef __ASSEMBLY__
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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extern struct page *empty_zero_page;
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extern void paging_init(void);
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#define ZERO_PAGE(vaddr) (empty_zero_page)
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#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
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#define pfn_pte(pfn,prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)))
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#define pte_none(pte) !(pte_val(pte))
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#define pte_clear(mm,addr,ptep) set_pte_at((mm),(addr),(ptep), __pte(0))
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#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
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static unsigned long pmd_page_vaddr(pmd_t pmd)
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{
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return ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK));
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}
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#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
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/*
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* Set a level 1 translation table entry, and clean it out of
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* any caches such that the MMUs can load it correctly.
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*/
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static inline void set_pmd(pmd_t * pmdp, pmd_t pmd)
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{
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*pmdp = pmd;
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#if !defined(CONFIG_CPU_DCACHE_DISABLE) && !defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
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__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (pmdp):"memory");
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__nds32__msync_all();
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__nds32__dsb();
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#endif
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}
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/*
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* Set a PTE and flush it out
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*/
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static inline void set_pte(pte_t * ptep, pte_t pte)
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{
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*ptep = pte;
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#if !defined(CONFIG_CPU_DCACHE_DISABLE) && !defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
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__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (ptep):"memory");
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__nds32__msync_all();
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__nds32__dsb();
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#endif
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}
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/*
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* The following only work if pte_present() is true.
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* Undefined behaviour if not..
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*/
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/*
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* pte_write: this page is writeable for user mode
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* pte_read: this page is readable for user mode
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* pte_kernel_write: this page is writeable for kernel mode
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*
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* We don't have pte_kernel_read because kernel always can read.
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*
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* */
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#define pte_present(pte) (pte_val(pte) & _PAGE_V)
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#define pte_write(pte) ((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_URW_KRW)
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#define pte_read(pte) (((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_UR_KR) || \
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((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_UR_KRW) || \
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((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_URW_KRW))
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#define pte_kernel_write(pte) (((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_URW_KRW) || \
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((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_UR_KRW) || \
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((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_KRW) || \
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(((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_XKRW) && pte_exec(pte)))
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#define pte_exec(pte) (pte_val(pte) & _PAGE_E)
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#define pte_dirty(pte) (pte_val(pte) & _PAGE_D)
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#define pte_young(pte) (pte_val(pte) & _PAGE_YOUNG)
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/*
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* The following only works if pte_present() is not true.
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*/
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#define pte_file(pte) (pte_val(pte) & _PAGE_FILE)
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#define pte_to_pgoff(x) (pte_val(x) >> 2)
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#define pgoff_to_pte(x) __pte(((x) << 2) | _PAGE_FILE)
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#define PTE_FILE_MAX_BITS 29
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#define PTE_BIT_FUNC(fn,op) \
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static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
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static inline pte_t pte_wrprotect(pte_t pte)
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{
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pte_val(pte) = pte_val(pte) & ~_PAGE_M_MASK;
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pte_val(pte) = pte_val(pte) | _PAGE_M_UR_KR;
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return pte;
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}
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static inline pte_t pte_mkwrite(pte_t pte)
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{
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pte_val(pte) = pte_val(pte) & ~_PAGE_M_MASK;
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pte_val(pte) = pte_val(pte) | _PAGE_M_URW_KRW;
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return pte;
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}
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PTE_BIT_FUNC(exprotect, &=~_PAGE_E);
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PTE_BIT_FUNC(mkexec, |=_PAGE_E);
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PTE_BIT_FUNC(mkclean, &=~_PAGE_D);
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PTE_BIT_FUNC(mkdirty, |=_PAGE_D);
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PTE_BIT_FUNC(mkold, &=~_PAGE_YOUNG);
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PTE_BIT_FUNC(mkyoung, |=_PAGE_YOUNG);
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/*
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* Mark the prot value as uncacheable and unbufferable.
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*/
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#define pgprot_noncached(prot) __pgprot((pgprot_val(prot)&~_PAGE_C_MASK) | _PAGE_C_DEV)
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#define pgprot_writecombine(prot) __pgprot((pgprot_val(prot)&~_PAGE_C_MASK) | _PAGE_C_DEV_WB)
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#define pmd_none(pmd) (pmd_val(pmd)&0x1)
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#define pmd_present(pmd) (!pmd_none(pmd))
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#define pmd_bad(pmd) pmd_none(pmd)
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#define copy_pmd(pmdpd,pmdps) set_pmd((pmdpd), *(pmdps))
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#define pmd_clear(pmdp) set_pmd((pmdp), __pmd(1))
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static inline pmd_t __mk_pmd(pte_t * ptep, unsigned long prot)
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{
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unsigned long ptr = (unsigned long)ptep;
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pmd_t pmd;
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/*
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* The pmd must be loaded with the physical
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* address of the PTE table
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*/
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pmd_val(pmd) = __virt_to_phys(ptr) | prot;
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return pmd;
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}
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#define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd)))
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/*
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* Permanent address of a page. We never have highmem, so this is trivial.
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|
*/
|
||
|
|
#define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT))
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Conversion functions: convert a page and protection to a page entry,
|
||
|
|
* and a page entry and page directory to the page they refer to.
|
||
|
|
*/
|
||
|
|
#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The "pgd_xxx()" functions here are trivial for a folded two-level
|
||
|
|
* setup: the pgd is never bad, and a pmd always exists (as it's folded
|
||
|
|
* into the pgd entry)
|
||
|
|
*/
|
||
|
|
#define pgd_none(pgd) (0)
|
||
|
|
#define pgd_bad(pgd) (0)
|
||
|
|
#define pgd_present(pgd) (1)
|
||
|
|
#define pgd_clear(pgdp) do { } while (0)
|
||
|
|
|
||
|
|
#define page_pte_prot(page,prot) mk_pte(page, prot)
|
||
|
|
#define page_pte(page) mk_pte(page, __pgprot(0))
|
||
|
|
/*
|
||
|
|
* L1PTE = $mr1 + ((virt >> PMD_SHIFT) << 2);
|
||
|
|
* L2PTE = (((virt >> PAGE_SHIFT) & (PTRS_PER_PTE -1 )) << 2);
|
||
|
|
* PPN = (phys & 0xfffff000);
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
|
||
|
|
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
||
|
|
{
|
||
|
|
const unsigned long mask = 0xfff;
|
||
|
|
pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
|
||
|
|
return pte;
|
||
|
|
}
|
||
|
|
|
||
|
|
extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
|
||
|
|
|
||
|
|
/* Encode and decode a swap entry.
|
||
|
|
*
|
||
|
|
* We support up to 32GB of swap on 4k machines
|
||
|
|
*/
|
||
|
|
#define __swp_type(x) (((x).val >> 2) & 0x7f)
|
||
|
|
#define __swp_offset(x) ((x).val >> 9)
|
||
|
|
#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 9) })
|
||
|
|
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
|
||
|
|
#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
|
||
|
|
|
||
|
|
/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
|
||
|
|
#define kern_addr_valid(addr) (1)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* We provide our own arch_get_unmapped_area to cope with VIPT caches.
|
||
|
|
*/
|
||
|
|
#define HAVE_ARCH_UNMAPPED_AREA
|
||
|
|
|
||
|
|
/*
|
||
|
|
* remap a physical address `phys' of size `size' with page protection `prot'
|
||
|
|
* into virtual address `from'
|
||
|
|
*/
|
||
|
|
|
||
|
|
#endif /* !__ASSEMBLY__ */
|
||
|
|
|
||
|
|
#endif /* _ASMNDS32_PGTABLE_H */
|