429 lines
10 KiB
C
429 lines
10 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2011 Samsung Electronics Co., Ltd.
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// http://www.samsung.com
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//
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// Copyright 2008 Openmoko, Inc.
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// Copyright 2008 Simtec Electronics
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// Ben Dooks <ben@simtec.co.uk>
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// http://armlinux.simtec.co.uk/
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//
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// Common Codes for S3C64XX machines
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/*
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* NOTE: Code in this file is not used when booting with Device Tree support.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/serial_core.h>
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#include <linux/serial_s3c.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/io.h>
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#include <linux/clk/samsung.h>
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#include <linux/dma-mapping.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <linux/irqchip/arm-vic.h>
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#include <clocksource/samsung_pwm.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/system_misc.h>
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#include "map.h"
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#include <mach/irqs.h>
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#include "regs-gpio.h"
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#include "gpio-samsung.h"
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#include "cpu.h"
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#include "devs.h"
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#include "pm.h"
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#include "gpio-cfg.h"
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#include "pwm-core.h"
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#include "regs-irqtype.h"
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#include "s3c64xx.h"
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#include "irq-uart-s3c64xx.h"
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/* External clock frequency */
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static unsigned long xtal_f __ro_after_init = 12000000;
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static unsigned long xusbxti_f __ro_after_init = 48000000;
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void __init s3c64xx_set_xtal_freq(unsigned long freq)
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{
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xtal_f = freq;
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}
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void __init s3c64xx_set_xusbxti_freq(unsigned long freq)
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{
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xusbxti_f = freq;
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}
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/* uart registration process */
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static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
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{
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s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
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}
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/* table of supported CPUs */
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static const char name_s3c6400[] = "S3C6400";
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static const char name_s3c6410[] = "S3C6410";
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static struct cpu_table cpu_ids[] __initdata = {
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{
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.idcode = S3C6400_CPU_ID,
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.idmask = S3C64XX_CPU_MASK,
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.map_io = s3c6400_map_io,
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.init_uarts = s3c64xx_init_uarts,
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.init = s3c6400_init,
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.name = name_s3c6400,
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}, {
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.idcode = S3C6410_CPU_ID,
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.idmask = S3C64XX_CPU_MASK,
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.map_io = s3c6410_map_io,
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.init_uarts = s3c64xx_init_uarts,
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.init = s3c6410_init,
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.name = name_s3c6410,
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},
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};
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/* minimal IO mapping */
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/*
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* note, for the boot process to work we have to keep the UART
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* virtual address aligned to an 1MiB boundary for the L1
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* mapping the head code makes. We keep the UART virtual address
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* aligned and add in the offset when we load the value here.
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*/
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#define UART_OFFS (S3C_PA_UART & 0xfffff)
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static struct map_desc s3c_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_SYS,
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.pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_MEM,
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.pfn = __phys_to_pfn(S3C64XX_PA_SROM),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
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.pfn = __phys_to_pfn(S3C_PA_UART),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)VA_VIC0,
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.pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)VA_VIC1,
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.pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_TIMER,
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.pfn = __phys_to_pfn(S3C_PA_TIMER),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C64XX_VA_GPIO,
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.pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C64XX_VA_MODEM,
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.pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_WATCHDOG,
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.pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_USB_HSPHY,
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.pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
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.length = SZ_1K,
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.type = MT_DEVICE,
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},
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};
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static struct bus_type s3c64xx_subsys = {
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.name = "s3c64xx-core",
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.dev_name = "s3c64xx-core",
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};
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static struct device s3c64xx_dev = {
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.bus = &s3c64xx_subsys,
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};
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static struct samsung_pwm_variant s3c64xx_pwm_variant = {
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.bits = 32,
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.div_base = 0,
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.has_tint_cstat = true,
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.tclk_mask = (1 << 7) | (1 << 6) | (1 << 5),
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};
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void __init s3c64xx_set_timer_source(enum s3c64xx_timer_mode event,
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enum s3c64xx_timer_mode source)
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{
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s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
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s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
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}
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void __init s3c64xx_timer_init(void)
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{
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unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
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IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
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IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
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};
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samsung_pwm_clocksource_init(S3C_VA_TIMER,
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timer_irqs, &s3c64xx_pwm_variant);
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}
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/* read cpu identification code */
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void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
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{
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/* initialise the io descriptors we need for initialisation */
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iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
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iotable_init(mach_desc, size);
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/* detect cpu id */
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s3c64xx_init_cpu();
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s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
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samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
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}
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static __init int s3c64xx_dev_init(void)
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{
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/* Not applicable when using DT. */
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if (of_have_populated_dt() || !soc_is_s3c64xx())
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return 0;
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subsys_system_register(&s3c64xx_subsys, NULL);
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return device_register(&s3c64xx_dev);
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}
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core_initcall(s3c64xx_dev_init);
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/*
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* setup the sources the vic should advertise resume
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* for, even though it is not doing the wake
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* (set_irq_wake needs to be valid)
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*/
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#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
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#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
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1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
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1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
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1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
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1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
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void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
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{
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s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS);
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printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
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/* initialise the pair of VICs */
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vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
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vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
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}
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#define eint_offset(irq) ((irq) - IRQ_EINT(0))
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#define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq)))
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static inline void s3c_irq_eint_mask(struct irq_data *data)
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{
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u32 mask;
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mask = __raw_readl(S3C64XX_EINT0MASK);
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mask |= (u32)data->chip_data;
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__raw_writel(mask, S3C64XX_EINT0MASK);
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}
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static void s3c_irq_eint_unmask(struct irq_data *data)
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{
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u32 mask;
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mask = __raw_readl(S3C64XX_EINT0MASK);
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mask &= ~((u32)data->chip_data);
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__raw_writel(mask, S3C64XX_EINT0MASK);
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}
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static inline void s3c_irq_eint_ack(struct irq_data *data)
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{
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__raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
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}
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static void s3c_irq_eint_maskack(struct irq_data *data)
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{
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/* compiler should in-line these */
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s3c_irq_eint_mask(data);
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s3c_irq_eint_ack(data);
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}
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static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
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{
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int offs = eint_offset(data->irq);
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int pin, pin_val;
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int shift;
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u32 ctrl, mask;
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u32 newvalue = 0;
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void __iomem *reg;
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if (offs > 27)
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return -EINVAL;
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if (offs <= 15)
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reg = S3C64XX_EINT0CON0;
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else
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reg = S3C64XX_EINT0CON1;
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switch (type) {
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case IRQ_TYPE_NONE:
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printk(KERN_WARNING "No edge setting!\n");
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break;
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case IRQ_TYPE_EDGE_RISING:
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newvalue = S3C2410_EXTINT_RISEEDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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newvalue = S3C2410_EXTINT_FALLEDGE;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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newvalue = S3C2410_EXTINT_BOTHEDGE;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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newvalue = S3C2410_EXTINT_LOWLEV;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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newvalue = S3C2410_EXTINT_HILEV;
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break;
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default:
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printk(KERN_ERR "No such irq type %d", type);
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return -1;
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}
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if (offs <= 15)
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shift = (offs / 2) * 4;
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else
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shift = ((offs - 16) / 2) * 4;
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mask = 0x7 << shift;
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ctrl = __raw_readl(reg);
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ctrl &= ~mask;
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ctrl |= newvalue << shift;
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__raw_writel(ctrl, reg);
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/* set the GPIO pin appropriately */
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if (offs < 16) {
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pin = S3C64XX_GPN(offs);
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pin_val = S3C_GPIO_SFN(2);
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} else if (offs < 23) {
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pin = S3C64XX_GPL(offs + 8 - 16);
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pin_val = S3C_GPIO_SFN(3);
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} else {
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pin = S3C64XX_GPM(offs - 23);
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pin_val = S3C_GPIO_SFN(3);
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}
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s3c_gpio_cfgpin(pin, pin_val);
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return 0;
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}
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static struct irq_chip s3c_irq_eint = {
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.name = "s3c-eint",
|
||
|
|
.irq_mask = s3c_irq_eint_mask,
|
||
|
|
.irq_unmask = s3c_irq_eint_unmask,
|
||
|
|
.irq_mask_ack = s3c_irq_eint_maskack,
|
||
|
|
.irq_ack = s3c_irq_eint_ack,
|
||
|
|
.irq_set_type = s3c_irq_eint_set_type,
|
||
|
|
.irq_set_wake = s3c_irqext_wake,
|
||
|
|
};
|
||
|
|
|
||
|
|
/* s3c_irq_demux_eint
|
||
|
|
*
|
||
|
|
* This function demuxes the IRQ from the group0 external interrupts,
|
||
|
|
* from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
|
||
|
|
* the specific handlers s3c_irq_demux_eintX_Y.
|
||
|
|
*/
|
||
|
|
static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
|
||
|
|
{
|
||
|
|
u32 status = __raw_readl(S3C64XX_EINT0PEND);
|
||
|
|
u32 mask = __raw_readl(S3C64XX_EINT0MASK);
|
||
|
|
unsigned int irq;
|
||
|
|
|
||
|
|
status &= ~mask;
|
||
|
|
status >>= start;
|
||
|
|
status &= (1 << (end - start + 1)) - 1;
|
||
|
|
|
||
|
|
for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
|
||
|
|
if (status & 1)
|
||
|
|
generic_handle_irq(irq);
|
||
|
|
|
||
|
|
status >>= 1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void s3c_irq_demux_eint0_3(struct irq_desc *desc)
|
||
|
|
{
|
||
|
|
s3c_irq_demux_eint(0, 3);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void s3c_irq_demux_eint4_11(struct irq_desc *desc)
|
||
|
|
{
|
||
|
|
s3c_irq_demux_eint(4, 11);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void s3c_irq_demux_eint12_19(struct irq_desc *desc)
|
||
|
|
{
|
||
|
|
s3c_irq_demux_eint(12, 19);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void s3c_irq_demux_eint20_27(struct irq_desc *desc)
|
||
|
|
{
|
||
|
|
s3c_irq_demux_eint(20, 27);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __init s3c64xx_init_irq_eint(void)
|
||
|
|
{
|
||
|
|
int irq;
|
||
|
|
|
||
|
|
/* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */
|
||
|
|
if (of_have_populated_dt() || !soc_is_s3c64xx())
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
|
||
|
|
irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
|
||
|
|
irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
|
||
|
|
irq_clear_status_flags(irq, IRQ_NOREQUEST);
|
||
|
|
}
|
||
|
|
|
||
|
|
irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
|
||
|
|
irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
|
||
|
|
irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
|
||
|
|
irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
arch_initcall(s3c64xx_init_irq_eint);
|