382 lines
14 KiB
Plaintext
382 lines
14 KiB
Plaintext
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Samsung GPIO and Pin Mux/Config controller
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Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware
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controller. It controls the input/output settings on the available pads/pins
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and also provides ability to multiplex and configure the output of various
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on-chip controllers onto these pads.
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Required Properties:
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- compatible: should be one of the following.
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- "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
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- "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
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- "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
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- "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
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- "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
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- "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
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- "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
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- "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
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- "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
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- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
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- "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
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- "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller.
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- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
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- "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller.
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- "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
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- "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller.
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- reg: Base address of the pin controller hardware module and length of
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the address space it occupies.
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- reg: Second base address of the pin controller if the specific registers
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of the pin controller are separated into the different base address.
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Eg: GPF[1-5] of Exynos5433 are separated into the two base address.
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- First base address is for GPAx and GPF[1-5] external interrupt
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registers.
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- Second base address is for GPF[1-5] pinctrl registers.
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pinctrl_0: pinctrl@10580000 {
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compatible = "samsung,exynos5433-pinctrl";
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reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
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wakeup-interrupt-controller {
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compatible = "samsung,exynos7-wakeup-eint";
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interrupts = <0 16 0>;
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};
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};
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- Pin banks as child nodes: Pin banks of the controller are represented by child
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nodes of the controller node. Bank name is taken from name of the node. Each
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bank node must contain following properties:
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- gpio-controller: identifies the node as a gpio controller and pin bank.
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- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
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binding is used, the amount of cells must be specified as 2. See the below
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mentioned gpio binding representation for description of particular cells.
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Eg: <&gpx2 6 0>
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<[phandle of the gpio controller node]
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[pin number within the gpio controller]
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[flags]>
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Values for gpio specifier:
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- Pin number: is a value between 0 to 7.
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- Flags: 0 - Active High
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1 - Active Low
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- Pin mux/config groups as child nodes: The pin mux (selecting pin function
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mode) and pin config (pull up/down, driver strength) settings are represented
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as child nodes of the pin-controller node. There should be at least one
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child node and there is no limit on the count of these child nodes. It is
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also possible for a child node to consist of several further child nodes
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to allow grouping multiple pinctrl groups into one. The format of second
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level child nodes is exactly the same as for first level ones and is
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described below.
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The child node should contain a list of pin(s) on which a particular pin
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function selection or pin configuration (or both) have to applied. This
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list of pins is specified using the property name "samsung,pins". There
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should be at least one pin specified for this property and there is no upper
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limit on the count of pins that can be specified. The pins are specified
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using pin names which are derived from the hardware manual of the SoC. As
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an example, the pins in GPA0 bank of the pin controller can be represented
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as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case.
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The format of the pin names should be (as per the hardware manual)
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"[pin bank name]-[pin number within the bank]".
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The pin function selection that should be applied on the pins listed in the
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child node is specified using the "samsung,pin-function" property. The value
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of this property that should be applied to each of the pins listed in the
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"samsung,pins" property should be picked from the hardware manual of the SoC
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for the specified pin group. This property is optional in the child node if
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no specific function selection is desired for the pins listed in the child
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node. The value of this property is used as-is to program the pin-controller
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function selector register of the pin-bank.
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The child node can also optionally specify one or more of the pin
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configuration that should be applied on all the pins listed in the
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"samsung,pins" property of the child node. The following pin configuration
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properties are supported.
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- samsung,pin-val: Initial value of pin output buffer.
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- samsung,pin-pud: Pull up/down configuration.
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- samsung,pin-drv: Drive strength configuration.
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- samsung,pin-pud-pdn: Pull up/down configuration in power down mode.
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- samsung,pin-drv-pdn: Drive strength configuration in power down mode.
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The values specified by these config properties should be derived from the
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hardware manual and these values are programmed as-is into the pin
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pull up/down and driver strength register of the pin-controller.
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Note: A child should include at least a pin function selection property or
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pin configuration property (one or more) or both.
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The client nodes that require a particular pin function selection and/or
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pin configuration should use the bindings listed in the "pinctrl-bindings.txt"
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file.
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External GPIO and Wakeup Interrupts:
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The controller supports two types of external interrupts over gpio. The first
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is the external gpio interrupt and second is the external wakeup interrupts.
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The difference between the two is that the external wakeup interrupts can be
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used as system wakeup events.
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A. External GPIO Interrupts: For supporting external gpio interrupts, the
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following properties should be specified in the pin-controller device node.
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- interrupts: interrupt specifier for the controller. The format and value of
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the interrupt specifier depends on the interrupt parent for the controller.
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In addition, following properties must be present in node of every bank
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of pins supporting GPIO interrupts:
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- interrupt-controller: identifies the controller node as interrupt-parent.
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- #interrupt-cells: the value of this property should be 2.
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- First Cell: represents the external gpio interrupt number local to the
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external gpio interrupt space of the controller.
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- Second Cell: flags to identify the type of the interrupt
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- 1 = rising edge triggered
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- 2 = falling edge triggered
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- 3 = rising and falling edge triggered
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- 4 = high level triggered
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- 8 = low level triggered
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B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
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child node representing the external wakeup interrupt controller should be
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included in the pin-controller device node.
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Only one pin-controller device node can include external wakeup interrupts
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child node (in other words, only one External Wakeup Interrupts
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pin-controller is supported).
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This child node should include following properties:
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- compatible: identifies the type of the external wakeup interrupt controller
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The possible values are:
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- samsung,s3c2410-wakeup-eint: represents wakeup interrupt controller
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found on Samsung S3C24xx SoCs except S3C2412 and S3C2413,
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- samsung,s3c2412-wakeup-eint: represents wakeup interrupt controller
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found on Samsung S3C2412 and S3C2413 SoCs,
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- samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller
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found on Samsung S3C64xx SoCs,
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- samsung,s5pv210-wakeup-eint: represents wakeup interrupt controller
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found on Samsung S5Pv210 SoCs,
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- samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
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found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs.
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- samsung,exynos7-wakeup-eint: represents wakeup interrupt controller
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found on Samsung Exynos7 SoC.
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- interrupts: interrupt used by multiplexed wakeup interrupts.
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In addition, following properties must be present in node of every bank
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of pins supporting wake-up interrupts:
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- interrupt-controller: identifies the node as interrupt-parent.
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- #interrupt-cells: the value of this property should be 2
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- First Cell: represents the external wakeup interrupt number local to
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the external wakeup interrupt space of the controller.
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- Second Cell: flags to identify the type of the interrupt
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- 1 = rising edge triggered
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- 2 = falling edge triggered
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- 3 = rising and falling edge triggered
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- 4 = high level triggered
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- 8 = low level triggered
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Node of every bank of pins supporting direct wake-up interrupts (without
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multiplexing) must contain following properties:
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- interrupts: interrupts of the interrupt parent which are used for external
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wakeup interrupts from pins of the bank, must contain interrupts for all
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pins of the bank.
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Aliases:
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All the pin controller nodes should be represented in the aliases node using
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the following format 'pinctrl{n}' where n is a unique number for the alias.
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Aliases for controllers compatible with "samsung,exynos7-pinctrl":
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- pinctrl0: pin controller of ALIVE block,
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- pinctrl1: pin controller of BUS0 block,
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- pinctrl2: pin controller of NFC block,
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- pinctrl3: pin controller of TOUCH block,
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- pinctrl4: pin controller of FF block,
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- pinctrl5: pin controller of ESE block,
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- pinctrl6: pin controller of FSYS0 block,
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- pinctrl7: pin controller of FSYS1 block,
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- pinctrl8: pin controller of BUS1 block,
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- pinctrl9: pin controller of AUDIO block,
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Example: A pin-controller node with pin banks:
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pinctrl_0: pinctrl@11400000 {
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x11400000 0x1000>;
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interrupts = <0 47 0>;
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/* ... */
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/* Pin bank without external interrupts */
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gpy0: gpy0 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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/* ... */
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/* Pin bank with external GPIO or muxed wake-up interrupts */
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gpj0: gpj0 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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/* ... */
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/* Pin bank with external direct wake-up interrupts */
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gpx0: gpx0 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
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<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
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#interrupt-cells = <2>;
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};
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/* ... */
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};
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Example 1: A pin-controller node with pin groups.
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#include <dt-bindings/pinctrl/samsung.h>
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pinctrl_0: pinctrl@11400000 {
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x11400000 0x1000>;
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interrupts = <0 47 0>;
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/* ... */
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uart0_data: uart0-data {
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samsung,pins = "gpa0-0", "gpa0-1";
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samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
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samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
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samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
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};
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uart0_fctl: uart0-fctl {
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samsung,pins = "gpa0-2", "gpa0-3";
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samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
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samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
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samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
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};
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uart1_data: uart1-data {
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samsung,pins = "gpa0-4", "gpa0-5";
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samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
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samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
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samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
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};
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uart1_fctl: uart1-fctl {
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samsung,pins = "gpa0-6", "gpa0-7";
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samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
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samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
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samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
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};
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i2c2_bus: i2c2-bus {
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samsung,pins = "gpa0-6", "gpa0-7";
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samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
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samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
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samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
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};
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sd4_bus8: sd4-bus-width8 {
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part-1 {
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samsung,pins = "gpk0-3", "gpk0-4",
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"gpk0-5", "gpk0-6";
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samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
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samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
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samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
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};
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part-2 {
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samsung,pins = "gpk1-3", "gpk1-4",
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"gpk1-5", "gpk1-6";
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samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
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samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
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samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
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};
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};
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};
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Example 2: A pin-controller node with external wakeup interrupt controller node.
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pinctrl_1: pinctrl@11000000 {
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x11000000 0x1000>;
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interrupts = <0 46 0>
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/* ... */
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wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <0 32 0>;
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};
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};
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Example 3: A uart client node that supports 'default' and 'flow-control' states.
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|
uart@13800000 {
|
||
|
|
compatible = "samsung,exynos4210-uart";
|
||
|
|
reg = <0x13800000 0x100>;
|
||
|
|
interrupts = <0 52 0>;
|
||
|
|
pinctrl-names = "default", "flow-control;
|
||
|
|
pinctrl-0 = <&uart0_data>;
|
||
|
|
pinctrl-1 = <&uart0_data>, <&uart0_fctl>;
|
||
|
|
};
|
||
|
|
|
||
|
|
Example 4: Set up the default pin state for uart controller.
|
||
|
|
|
||
|
|
static int s3c24xx_serial_probe(struct platform_device *pdev) {
|
||
|
|
struct pinctrl *pinctrl;
|
||
|
|
|
||
|
|
/* ... */
|
||
|
|
|
||
|
|
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
||
|
|
}
|
||
|
|
|
||
|
|
Example 5: A display port client node that supports 'default' pinctrl state
|
||
|
|
and gpio binding.
|
||
|
|
|
||
|
|
display-port-controller {
|
||
|
|
/* ... */
|
||
|
|
|
||
|
|
samsung,hpd-gpio = <&gpx2 6 0>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&dp_hpd>;
|
||
|
|
};
|
||
|
|
|
||
|
|
Example 6: Request the gpio for display port controller
|
||
|
|
|
||
|
|
static int exynos_dp_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
int hpd_gpio, ret;
|
||
|
|
struct device *dev = &pdev->dev;
|
||
|
|
struct device_node *dp_node = dev->of_node;
|
||
|
|
|
||
|
|
/* ... */
|
||
|
|
|
||
|
|
hpd_gpio = of_get_named_gpio(dp_node, "samsung,hpd-gpio", 0);
|
||
|
|
|
||
|
|
/* ... */
|
||
|
|
|
||
|
|
ret = devm_gpio_request_one(&pdev->dev, hpd_gpio, GPIOF_IN,
|
||
|
|
"hpd_gpio");
|
||
|
|
/* ... */
|
||
|
|
}
|