130 lines
3.0 KiB
YAML
130 lines
3.0 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2021 Microchip Technology, Inc.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/microchip,xisc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip eXtended Image Sensor Controller (XISC)
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maintainers:
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- Eugen Hristev <eugen.hristev@microchip.com>
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description: |
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The eXtended Image Sensor Controller (XISC) device provides the video input capabilities for the
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Microchip AT91 SAM family of devices.
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The XISC has a single internal parallel input that supports RAW Bayer, RGB or YUV video.
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The source can be either a demuxer from a CSI2 type of bus, or a simple direct bridge to a
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parallel sensor.
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The XISC provides one clock output that is used to clock the demuxer/bridge.
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properties:
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compatible:
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const: microchip,sama7g5-isc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: hclock
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'#clock-cells':
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const: 0
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clock-output-names:
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const: isc-mck
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microchip,mipi-mode:
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type: boolean
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description:
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As the XISC is usually connected to a demux/bridge, the XISC receives
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the same type of input, however, it should be aware of the type of
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signals received. The mipi-mode enables different internal handling
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of the data and clock lines.
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port:
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$ref: /schemas/graph.yaml#/$defs/port-base
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description:
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Input port node, single endpoint describing the input pad.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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properties:
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bus-type:
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enum: [5, 6]
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remote-endpoint: true
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bus-width:
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enum: [8, 9, 10, 11, 12]
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default: 12
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hsync-active:
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enum: [0, 1]
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default: 1
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vsync-active:
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enum: [0, 1]
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default: 1
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pclk-sample:
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enum: [0, 1]
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default: 1
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required:
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- remote-endpoint
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- bus-type
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additionalProperties: false
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additionalProperties: false
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- clock-output-names
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- port
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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xisc: xisc@e1408000 {
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compatible = "microchip,sama7g5-isc";
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reg = <0xe1408000 0x2000>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 56>;
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clock-names = "hclock";
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#clock-cells = <0>;
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clock-output-names = "isc-mck";
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port {
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xisc_in: endpoint {
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bus-type = <5>; /* Parallel */
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remote-endpoint = <&csi2dc_out>;
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hsync-active = <1>;
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vsync-active = <1>;
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bus-width = <12>;
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};
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};
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};
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