47 lines
1.5 KiB
Plaintext
47 lines
1.5 KiB
Plaintext
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* ARC-HS Interrupt Distribution Unit
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This optional 2nd level interrupt controller can be used in SMP configurations
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for dynamic IRQ routing, load balancing of common/external IRQs towards core
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intc.
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Properties:
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- compatible: "snps,archs-idu-intc"
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- interrupt-controller: This is an interrupt controller.
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- #interrupt-cells: Must be <1> or <2>.
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Value of the first cell specifies the "common" IRQ from peripheral to IDU.
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Number N of the particular interrupt line of IDU corresponds to the line N+24
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of the core interrupt controller.
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The (optional) second cell specifies any of the following flags:
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- bits[3:0] trigger type and level flags
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1 = low-to-high edge triggered
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2 = NOT SUPPORTED (high-to-low edge triggered)
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4 = active high level-sensitive <<< DEFAULT
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8 = NOT SUPPORTED (active low level-sensitive)
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When no second cell is specified, the interrupt is assumed to be level
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sensitive.
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The interrupt controller is accessed via the special ARC AUX register
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interface, hence "reg" property is not specified.
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Example:
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core_intc: core-interrupt-controller {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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interrupt-parent = <&core_intc>;
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#interrupt-cells = <1>;
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};
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some_device: serial@c0fc1000 {
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interrupt-parent = <&idu_intc>;
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interrupts = <0>; /* upstream idu IRQ #24 */
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};
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