61 lines
2.0 KiB
Plaintext
61 lines
2.0 KiB
Plaintext
|
* Rockchip RK3308 Clock and Reset Unit
|
||
|
|
|
||
|
|
The RK3308 clock controller generates and supplies clock to various
|
||
|
|
controllers within the SoC and also implements a reset controller for SoC
|
||
|
|
peripherals.
|
||
|
|
|
||
|
|
Required Properties:
|
||
|
|
|
||
|
|
- compatible: CRU should be "rockchip,rk3308-cru"
|
||
|
|
- reg: physical base address of the controller and length of memory mapped
|
||
|
|
region.
|
||
|
|
- #clock-cells: should be 1.
|
||
|
|
- #reset-cells: should be 1.
|
||
|
|
|
||
|
|
Optional Properties:
|
||
|
|
|
||
|
|
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||
|
|
If missing, pll rates are not changeable, due to the missing pll lock status.
|
||
|
|
|
||
|
|
Each clock is assigned an identifier and client nodes can use this identifier
|
||
|
|
to specify the clock which they consume. All available clocks are defined as
|
||
|
|
preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
|
||
|
|
used in device tree sources. Similar macros exist for the reset sources in
|
||
|
|
these files.
|
||
|
|
|
||
|
|
External clocks:
|
||
|
|
|
||
|
|
There are several clocks that are generated outside the SoC. It is expected
|
||
|
|
that they are defined using standard clock bindings with following
|
||
|
|
clock-output-names:
|
||
|
|
- "xin24m" - crystal input - required,
|
||
|
|
- "xin32k" - rtc clock - optional,
|
||
|
|
- "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in",
|
||
|
|
"mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in",
|
||
|
|
"mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional,
|
||
|
|
- "mac_clkin" - external MAC clock - optional
|
||
|
|
|
||
|
|
Example: Clock controller node:
|
||
|
|
|
||
|
|
cru: clock-controller@ff500000 {
|
||
|
|
compatible = "rockchip,rk3308-cru";
|
||
|
|
reg = <0x0 0xff500000 0x0 0x1000>;
|
||
|
|
rockchip,grf = <&grf>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
#reset-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
Example: UART controller node that consumes the clock generated by the clock
|
||
|
|
controller:
|
||
|
|
|
||
|
|
uart0: serial@ff0a0000 {
|
||
|
|
compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
|
||
|
|
reg = <0x0 0xff0a0000 0x0 0x100>;
|
||
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
||
|
|
clock-names = "baudclk", "apb_pclk";
|
||
|
|
reg-shift = <2>;
|
||
|
|
reg-io-width = <4>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|